SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
71
-
www.acromag.com
8.5 Field I/O
8.6 PCIe Bus Specifications
Compatibility
Conforms to PCI Express Base Specification, Revision 2.1
Line Speed
Gen1 (2.5Gbps) Available through system connector
Lane Operation
1-Lane
1M Byte Memory Space
Base Address Register (BAR0) to Zynq DMA Registers
32K Byte Memory Space
Base Address Register (BAR1) to Programmable Logic Register Space
64K Byte Memory Space
Base Address Register (BAR2) to DDR Memory Space
Table 8.6 PCIe Bus Data Rates
PCIe Gen 1 (1 lane)
Giga bit / second
Bytes / second
Signaling Rate
2.5 Gb/s
312 Mbyte/s
Ideal Rate
1
2 Gb/s
250 Mbyte/s
Header Burden plus 4byte
Sample Rate
2
0.332 Gb/s
41.6 Mbyte/s
Actual Measured 4 Byte
Read Rate
3
0.019 Gb/s
2.35 Mbytes/s
Actual Measured DMA 4
Byte Read Rate
4
0.327 Gb/s
40.9 Mbyte/s
Actual Measured 4 Byte
Write Rate
5
0.320 Gb/s
40 Mbyte/s
Note 1:
PCIe x1 Gen 1 = 2.5GT/s (with 10-bit encoding we have a 20% loss in
possible throughput due to encoding) giving 2.0 G bits/sec or 250M Bytes/sec.
Gigabit Ethernet Interface (J7)
Zynq processor system is equipped with a gigabit Ethernet controller. The
Zynq module provides the external PHY device (Marvell 88E1512-A0-
nnp2I000). The Zynq controller uses a media independent interface
(RGMII).
Marvell
88E1512-A0-nnp2I000
The transceiver implements the Ethernet physical layer portion of the
1000BASE-T, 100BASE-TX, and 10BASE-T standards. The device supports
RGMII (Reduced pin count GMII for direct connection) to Copper.
The external magnetics and RJ45 (J7) are provided on the breakout panel.
Interrupts
20 channels of interrupts may be configured for high-to-low, low-to- high,
and change-of-state event types.
