SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
41
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www.acromag.com
The GIC passed interrupt onto PCIe via initiating of a software generated
interrupt. This is accomplished with write to address 0xFD0F0070 with a
value of 0x8 to cause this software generated interrupt. See additional
documentation available in the Xilinx register user guide ug1087. The
AXIPCIE_DMA_DMA_CHANNEL_PCIE_INTERRUPT_ASSERT register is
documented in this Xilinx register user guide.
Viewing the Address Editor
Click on the “Address Editor” tab to open the Address editor.
The figure below shows the Address Editor tab of the Block Design view. The
offset address and block size for each peripheral can be set using this editor.
This table shows the master interfaces of each peripheral and lists the
devices that each can access along with the base addresses.
The offset address and size corresponding to the M01_AXI, BRAM, and
system management wizard are shown below. These addresses correspond
to those given in the user’s manual.
