SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
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www.acromag.com
5.1.2 APZU Programmable Logic Block Design Constraints
The APZU_physical.xdc is the design constraints file and can be found in the
constrs_1 folder. This file assigns the FPGA I/O signals to pins on the APZU
device. The 3.3 volt signals are assigned to Bank 26 pins and the 1.8 volt
signals are assigned to Bank 65 pins. It is in this file that the IOSTANDARD is
selected.
set_property IOSTANDARD LVCMOS33 [get_ports B26_TTL0]
The Slew rate, drive strength, if pull-up or pull-down resistor can also be set
in this file.
# set_property Output Slew Rate Control
# set_property SLEW FAST|SLOW [get_ports B26_TTL0]
set_property SLEW FAST [get_ports B26_TTL0]
# set_property Output Drive Strength in
# set_property DRIVE 4|8|12|16 [get_ports B26_TTL0]
set_property DRIVE 12 [get_ports B26_TTL0]
# set_property Pull-up, Pull-down, and Keeper
# set_property PULLTYPE PULLUP|PULLDOWN|KEEPER [get_ports]
set_property PULLTYPE PULLUP [get_ports B26_TTL0]
5.1.3 APZU Programmable Logic Block FPGA Configuration
In Zynq Ult boards such as the Zynq Ult MPSoC APZU, the
QSPI Flash is connected to the PS portion of the device and does not have a
direct physical connection to the PL side
.
In such configurations, it is not
possible to write a bitstream (.mcs file) directly to the flash via the Hardware
Manager. In fact, when attempting to configure the bitstream to be loaded
via QSPI, Vivado will only make the Boot via JTAG option available, as it
knows that there is no flash available in the PL.
In order to configure and boot such devices via Flash, the PS portion of the
device must be booted (even if it is not desired or will not be used in the
actual project), in order to allow the bitstream to be transmitted from the
Flash to reach the PL through the MIO pins.
The process requires having Zynq MPSoC block in Vivado Block Design in
order to include the PS in the project, and using the SDK to create a First
Stage Boot Loader (FSBL) for the PS, an optional PS application, and finally
