SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
40
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www.acromag.com
The M01_AXI port is configured as 32-bit data, 32-bit address, AXI lite
interface.
Interrupt from PL to PS system
The interrupt signal (interrupt_req) generated by the M01_AXI.vhd VHD file
is enabled for input to the ARM Cortex processor system by selecting
IRQ0[0-7] to 1 as described below.
Double select Zynq block in Block Design
Select PS-PL Configuration
Under PL to PS the IRQ0[0-7] is set to 1 as seen below.
The Zynq GIC (generic interrupt controller) receives PL to PS interrupt on
pl_ps_irq0. The Cortex-A53 MPCore uses an external generic interrupt
controller GIC-400 to support interrupts.
