Acromag APZU AcroPack Series User Manual Download | Manualshive

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SERIES APZU+ ACROPACK

USER’S MANUAL

Acromag, Inc. Tel: 248-295-0310 -

36

-

www.acromag.com

The M01_AXI port is configured as 32-bit data, 32-bit address, AXI lite
interface.

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Summary of Contents for APZU AcroPack Series

Page 1: ...Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 2020 Acromag Inc Printed in the USA Data and specifications are...

Page 2: ...Features 5 1 3 3 Key Features PCIe Interface 6 Figure 1 Block Diagram Model APZU 303 7 Figure 2 Block Diagram Model APZU 301 304 8 1 4 Signal Interface Products 8 1 5 Software Support 8 Windows 9 VxWo...

Page 3: ...H L Configuration Register Read Write BAR1 0x0000 0014 21 Interrupt Polarity Registers Read Write BAR1 0x0000 0018 22 Interrupt Status Register Read Write BAR1 0x0000 001C 22 RS485 Data Registers Read...

Page 4: ...EM BARE METAL SOFTWARE 58 6 1 PCIe Software 58 6 2 Ethernet Bare Metal Software 61 6 3 IIC Bare Metal Software 62 6 4 USB Bare Metal Software 63 6 5 LED Bare Metal Software 67 7 0 SERVICE AND REPAIR 6...

Page 5: ...er Acromag assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may...

Page 6: ...s The key information resulting from the parallel processing can then be passed to the ARM processing system for further manipulation and processing The APZU utilizes state of the art Surface Mounted...

Page 7: ...hernet Gigabit Ethernet over copper wire 1000BASE T LPDDR4 Storage Memory Provides 2 Giga Byte 512Mbit x 32 of LPDDR4 Memory USB Peripheral Port USB 2 0 Transceiver USB UART provides a Zynq debug term...

Page 8: ...l APZU 303 Quad SPI Flash 64MB 512Mb LPDDR4 2 GByte 512 x 32 Ethernet MAC Power Chip MPSoC XCZU3CG Programmable Logic PL PCIe X1 lane Ethernet 10 100 1000 USB 2 0 USB UART Boot Mode SW2 AcroPack I O 5...

Page 9: ...riers The breakout panel and short 68 pin male to male 1 foot cable will bring an ethernet port USB 2 0 port UART to USB port digital I O at jumper blocks and power and reset buttons out to the field...

Page 10: ...Model APSW API VXW is composed of VxWorks real time operating system libraries for all AcroPack modules VPX I O board products and PCIe I O Cards The software is implemented as a library of C functio...

Page 11: ...ioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2 1 Unpacking a...

Page 12: ...above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful considerati...

Page 13: ...anel Acromag part number 5028 626 For the APZU 303 these signals include 20 TTL three RS485 signal pairs UART to USB port USB 2 0 Ethernet via RJ 45 push button reset and power on push button Table 2...

Page 14: ...O45_UART1_RX J6 49 57 USB_UART1_CTS USB_UART1_CTS J6 16 62 USB_UART1_RTS USB_UART1_RTS J6 50 61 ULPIO_D_P ULPIO_D_P J5 17 66 ULPIO_D_N ULPIO_D_N J5 51 65 ULPIO_VBUS ULPIO_VBUS J5 18 70 GND GND GND P2...

Page 15: ...ments Power supplies 5 12 and 12 Volt have been assigned to pins that are reserved in the mini PCIe specification The Present signal is grounded on the AP module In addition COEX1 COEX2 wireless trans...

Page 16: ...nal COEX1 COEX2 UIM_C4 UIM_C8 have been repurposed for JTAG Note 2 5 12 and 12 Volt power supplies have been assigned to pins that are reserved in the mini PCIe specification Note 3 All 3 3Vaux power...

Page 17: ...em software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base addre...

Page 18: ...nq DMA registers The PCIe bus decodes 1M bytes for BAR0 for this memory space This board is allocated a 32K byte block of memory BAR1 to access the programmable logic registers The PCIe bus decodes 32...

Page 19: ...lt value logic low BAR1 Base Address Bit s Description 0x0000 0000 31 0 Global Interrupt Register 0x0000 0004 31 0 Location in System Register 0x0000 0008 31 0 Digital Input Output Register 0x0000 000...

Page 20: ...disable board interrupts Read Write Bit 0 Disabled 1 Enabled 1 Interrupt Pending Status Bit This bit can be read to determine the interrupt pending status of the AP module When this bit is logic 1 an...

Page 21: ...al register is used to monitor read or set write channels 0 through 19 Channels 0 to 19 are accessed at the carrier base address 0x0000_0008 via data bits 0 to 19 The unused upper 12 bits of this regi...

Page 22: ...nnels A 0 bit selects interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1...

Page 23: ...its are set to 0 following a reset which means that the inputs will cause interrupts when they are below logic low threshold provided they are enabled for interrupt on level Interrupt Status Register...

Page 24: ...ing to this register is possible via 32 bit 16 bit or 8 bit data transfers Firmware Revision Register Read Only BAR1 0x0000 0200 This is a read only register The ASCII code representing the current re...

Page 25: ...8 Maximum VCCAUX 0x0000_2490 Minimum Temperature 0x0000_2494 Minimum VCCINT 0x0000_2498 Minimum VCCAUX Table 3 7 FPGA Voltage and Temperature Range Symbol Minimum Typical Maximum Vccint 0 95 1 0 1 05...

Page 26: ...n only be written by the Zynq processor The Quad SPI device is not accessible from the programmable logic side Single slave select 4 bit I O interface to Zynq chip Quad SPI Controller as alternative b...

Page 27: ...he field I O interface to the carrier board is provided through connector P2 refer to Table 2 1 4 2 Digital Interface Logic The Zynq UltraScale Programmable Logic PL provides two types of I O banks Hi...

Page 28: ...Quad SPI Flash The APZU provides a 512 Mbit 64 Mbyte Nor Flash device MT25QL512ABBIEW9 Single slave select 4 bit I O interface to Zynq chip Quad SPI Controller as alternative boot source Memory space...

Page 29: ...idge using four signal pins Transmit TX Receive RX Request to Send RTS and Clear to Send CTS The UART to USB TX and RX pins are routed from Zynq PS MIO44 and MIO45 The RTS and CTS signals are driven b...

Page 30: ...ignals A2 A1 A0 are used to set the value that is to be looked for on the three least significant bits b3 b2 b1 of the 7 bit device select code User LEDS The APZU provides two user controllable LEDs c...

Page 31: ...module this real time clock does not operate or maintain time when module is power down See chapter 7 of Xilinx user guide UG1085 for more information on the real time clock Reset The APZU Reset is m...

Page 32: ...an FPGA This combination of tools enables hardware and software application design code execution and debug and transfer of the design onto APZU board for verification and validation 5 0 1 APZU Testi...

Page 33: ...design that provides host access to the hardware digital I O on the AP module The example design is intended to be a starting point from which customers will develop their customized applications The...

Page 34: ...P Integrator block diagram The VHDL source files are listed below These VHDL file can be seen in the project hierarchy in the sources box below At the highest level of the hierarchy is the APZU_top vh...

Page 35: ...oC System Management Wizard Block Memory Generator and the M01_AXI The M01_AXI interface connects to the Acromag custom VHDL code The M01_AXI AXI_ACLK AXI_RESETn signals are brought out with the Creat...

Page 36: ...ACK USER S MANUAL Acromag Inc Tel 248 295 0310 35 www acromag com The Block Memory Generator is configured as a True Dual Port RAM The AXI_ACLK is configured as a 100MHz clock and associated with the...

Page 37: ...SERIES APZU ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 36 www acromag com The M01_AXI port is configured as 32 bit data 32 bit address AXI lite interface...

Page 38: ...SERIES APZU ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 37 www acromag com The AXI reset signal was also made available to the top level design The AXI_RESETn signal is defined as shown below...

Page 39: ...peripherals enabled include QSPI using MIO pins 0 to 5 SD card using MIO pins 13 to 24 I2C using MIO pins 8 and 9 GPO5 MIO37 UART 1 using MIO pins 44 and 45 GEM3 MIO64 to 75 USB 0 MIO52 to 63 one lan...

Page 40: ...USER S MANUAL Acromag Inc Tel 248 295 0310 39 www acromag com In the Zynq block design window select Advanced Configuration Expand the UART Baud Rate Selection section and notice that the UART1 Baud r...

Page 41: ...ed by the M01_AXI vhd VHD file is enabled for input to the ARM Cortex processor system by selecting IRQ0 0 7 to 1 as described below Double select Zynq block in Block Design Select PS PL Configuration...

Page 42: ..._ASSERT register is documented in this Xilinx register user guide Viewing the Address Editor Click on the Address Editor tab to open the Address editor The figure below shows the Address Editor tab of...

Page 43: ...When we first generated the bitstream the tool automatically generated the output products for us If you have modified the Block Design the tool should recognize that the Block Design is newer than th...

Page 44: ...click OK The design_1_wrapper vhd file can be found in the sources_1 imports hdl folder The design_1_wrapper vhd created shows how a component can be added to the top level design file APZU_top vhd Se...

Page 45: ...rdware step is only required if an update to the existing Vivado design has been made In Vivado select File Export Export Hardware Platform Check Fixed Select Next Select Include Bitstream Click Next...

Page 46: ...PULLUP PULLDOWN KEEPER get_ports set_property PULLTYPE PULLUP get_ports B26_TTL0 5 1 3 APZU Programmable Logic Block FPGA Configuration In Zynq UltraScale boards such as the Zynq UltraScale MPSoC APZU...

Page 47: ...cused special tools to configure FPGAs Bootable image creation Flash programming Script based command line tool When you create the platform in Vitis IDE using APZU_top xsa the ZIP file automatically...

Page 48: ...ce path to your project file Alternately you can open the Vitis IDE with a default workspace and later switch it to the correct workspace by selecting File Switch Workspace and then selecting the work...

Page 49: ...SERIES APZU ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 48 www acromag com Browse to the APZU_top xsa file in the myVitis folder select open Select Finish...

Page 50: ...ZU ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 49 www acromag com The Vitis IDE generates the platform The files that are generated are displayed in the explorer window as shown in the followi...

Page 51: ...and psu_cortexa53_0 domain also added to the platform We can add multiple domains to platform Add the following libraries by modifying the standalone on psu_cortexa53_0 domain a Select Board Support P...

Page 52: ...UAL Acromag Inc Tel 248 295 0310 51 www acromag com Now build the hardware by right clicking on APZU_wrapper Build project The hardware platform is ready You can create applications using this platfor...

Page 53: ...www acromag com Create a new Application Select psu_corexa53_0 as seen below Select File New Application Project Select Next Select APZU_wrapper custom as Platform Select Next Enter the Application P...

Page 54: ...SERIES APZU ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 53 www acromag com With standalone on psu_cortexa53_0 hi lighted Select Next...

Page 55: ...APZU_Example Create Boot Image This will preload the First Stage Boot Loader FSBL ELF bitstream and Application ELF images The order of the files is important The FSBL is first followed by the bitstre...

Page 56: ...626 contains a Silicon Labs CP2103GM USB to UART bridge device This device handles connection from the APZU device to a host computer with a USB cable Connect the UART cable to the Breakout board Sil...

Page 57: ...ager Select Device Manager Under Ports expand and look for USB Serial Port device Steps to Program the Flash In Vitis IDE on the top bar menu select Xilinx Program Flash Fill in the information for th...

Page 58: ...SERIES APZU ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 57 www acromag com Test boot from flash Set Dip switch with only switch 2 OFF all others ON position...

Page 59: ...mple program The APZU_Example program will display the prompts shown below As seen below the APZU_Example application allows the individual interfaces to be run independently 6 1 PCIe Software The APZ...

Page 60: ...registers 0 and 1 The DMA scratchpad registers 0 and 1 are at BAR0 0x50 and 0x54 respectively Host then sends an interrupt to APZU Write BAR0 0x74 using the PCIe to AXI Interrupt register 5 Once the...

Page 61: ...MANUAL Acromag Inc Tel 248 295 0310 60 www acromag com The print statements from the bare metal application running on the APZU are seen on a putty terminal The host example design application prompts...

Page 62: ...e host system run a ping test by entering Ping 192 168 1 10 The ethernet MAC is resident in the Zynq and interfaces to the PHY device via a RGMII system interface The magnetics and RJ 45 are resident...

Page 63: ...sing and general call address are not supported The default device address is 0x5E though it can be modified by programming The programming registers are located in device address 0x38 which cannot be...

Page 64: ...data could be moved to the on board APZU DDR memory Run application menu item 4 below The application will display Mass Storage Device Start It is the UART Com port that provides the following display...

Page 65: ...SERIES APZU ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 64 www acromag com If USB Mass Storage Device is double selected it will show the following...

Page 66: ...Inc Tel 248 295 0310 65 www acromag com The host PC will ask to format the drive Enter a Volume label and start the format operation As a test a text file can be moved to the newly formatted drive Sel...

Page 67: ...owered up USB 5 volts will interfere with power up sequence requirements of the APZU Disconnect USB port when not in use Test by moving a file like the Purchasing Tracker Open Items xlsx file shown be...

Page 68: ...test the LEDs is given below ConfigPtr XGpioPs_LookupConfig GPIO_DEVICE_ID XGpioPs_CfgInitialize Gpio ConfigPtr ConfigPtr BaseAddr XGpioPs_SetDirectionPin Gpio 47 1 XGpioPs_SetOutputEnablePin Gpio 47...

Page 69: ...CAUTION POWER MUST BE TURNED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the documentati...

Page 70: ...422 40oC to 75oC1 2 APZU 3041 14 LVDS I O 40oC to 75oC1 2 Note 1 A minimum airflow of 400LFM is recommended Note 2 Do not run the module without the heatsink Running the module without a heatsink will...

Page 71: ...half sine 18 shocks at 6 orientations for both test levels 8 3 5 EMC Directives The AcroPack complies with EMC Directive 2004 108 EC Immunity per EN 61000 6 2 Electrostatic Discharge Immunity ESD per...

Page 72: ...3 0 019 Gb s 2 35 Mbytes s Actual Measured DMA 4 Byte Read Rate4 0 327 Gb s 40 9 Mbyte s Actual Measured 4 Byte Write Rate5 0 320 Gb s 40 Mbyte s Note 1 PCIe x1 Gen 1 2 5GT s with 10 bit encoding we h...

Page 73: ...c A read operation starts with a host read request The AcroPack must process the read and fetch the data and then generated the completion back to the host The host then sends a message back that says...

Page 74: ...e Power Down Type SRAM SDRAM etc Size User Modifiable Yes No Function Process to Sanitize Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained whe...

Page 75: ...ag com Revision History The revision history for this document is summarized in the table below Release Date mm dd yyyy Version EGR DOC Description of Revision 7 23 2020 Preliminary LMP LMP Preliminar...

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