SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
26
-
www.acromag.com
4.0 THEORY OF OPERATION
This section provides a description of the basic functionality of the circuitry
used on the board. Refer to the Block Diagram shown in Figure 1 and 2, in
section 1, as you review this material.
4.1 AcroPack Operation
The APZU+ is built around a digital Xilinx Ult Zynq chip that provides
I/O interface and configuration functions.
The PCIe bus interface logic is embedded within the processor system of the
Zynq chip. The Zynq provides support for PCIe commands, including
configuration read/write, and memory read/write. In addition, the PCIe
target interface uses BAR1 32K memory space for register access over the
M01_AXI interface. In addition, a 64K byte BAR2 memory space provides
access to the DDR memory.
The Zynq device provides the control signals required to operate the board.
It decodes the selected addresses and control signals. It also returns the
acknowledgement messages required by the carrier/CPU board per the PCIe
specification. The program for the Zynq is stored in separate Flash memory
and loaded upon power-up.
The field I/O interface to the carrier board is provided through connector P2
(refer to Table 2.1).
4.2 Digital Interface Logic
The Zynq Ult Programmable Logic (PL) provides two types of I/O
banks: High-density (HD) banks and High-performance (HP) banks. The HD
bank is used on the APZU-303 module which supports 3.3 volt LVTTL and
LVCMOS. HP banks are routed to the APZU-301 and APZU-304 models which
provide 1.8 volt LVTTL and LVDS respectively.
Model APZU-301
28 TTL Signals (1.8 volt)
Model APZU-304
14 LVDS Signals
(See Xilinx UG571 UltraScale
Architecture SelectIO
Resources)
Digital input channels of this model can be configured to generate interrupts
for Change-Of-State (COS) and input level (polarity) match conditions for all
input channels.
All I/O signals originate from bank 65 of the Zynq chip. Back 65 is powered
by 1.8 volts. The signals from Bank 65 are High-performance (HP) I/O
Resources. HP I/O is designed to support high-speed interfaces. Bank 65 I/O
signals will support LVDS I/O standard, and LVCMOS18. These signals can be
used as input, output, or bidirectional.
Xilinx developed digitally controlled impedance (DCI) technology to control
output impedance of a driver, or to add parallel termination at a receiver.
With LVDS input an optional internal differential termination in the XDC file
set DIFF_TERM_ADV = TERM_100 or DIFF_TERM = TRUE.
