Acromag AcroPack AP522 User Manual Download

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AP522 ACROPACK

USER

’S MANUAL

Acromag, Inc. Tel: 248-295-0310

- 2 - http://www.acromag.com

- 2 -

www.acromag.com

Table 2.2: Logic Interface Connections ........................................................................................ 14

3.0 PROGRAMMING INFORMATION ........................................................................... 16

3.1 PCI Configuration Registers ......................................................................................... 16

Table 3.1 PCI Configuration Registers ......................................................................................... 17

3.2 UART and Device Configuration Registers ................................................................... 17

Table 3.2 UART and Device Configuration Registers ................................................................... 18

Table 3.3 Device Configuration Registers in Byte Alignment ...................................................... 19

Table 3.4 Device Configuration Registers in DWORD Alignment ................................................ 20

3.2.1 The Global Interrupt Registers

–

INT0, INT1, INT2 and INT3 .......................................................20

Table 3.5 UART Channel Interrupt Source Encoding ................................................................... 21

3.2.1.1 Interrupt Clearing .......................................................................................................... 21

3.2.2 General Purpose 16-bit Timer/Counter [TimerMSB, TimerLSB, TIMER, TIMECNTL] ...................21

3.2.2.1 TIMERMSB[31:24] and TIMERLSB[23:16] ...................................................................... 21

3.2.2.2 TIMERCNTL[7:0] Register ............................................................................................... 22

Table 3.6 Timer Control Register ................................................................................................. 22

3.2.2.3 Timer Operation ............................................................................................................ 22

3.2.3 8XMODE[7:0] (default 0x00) ......................................................................................................23

3.2.4 4XMODE[15:8] (default 0x00) ....................................................................................................24

3.2.5 RESET[23:16] (default 0x00).......................................................................................................24

3.2.6 SLEEP[31:24] (default 0x00) .......................................................................................................24

3.2.7 DVID[15:8] .................................................................................................................................25

3.2.8 DREV[7:0] ..................................................................................................................................25

3.2.9 REGB[23:16] (default 0x00)........................................................................................................25

Table 3.7 REGB Register .............................................................................................................. 25

3.2.10 MPIO Registers ........................................................................................................................25

3.3 Transmit and Receive Data ......................................................................................... 26

3.3.1 FIFO Data Loading and Unloading in 32-bit Format ....................................................................26

3.3.2 FIFO Data Loading/Unloading Through the UART Channel Registers, THR and RHR, in 8-Bit
Format .................................................................................................................................................27

3.4 UART Channel Configuration Registers ........................................................................ 27

Table 3.8 UART Channel Configuration Registers ........................................................................ 27

3.4.1 Receiver .....................................................................................................................................28

3.4.2 Transmitter ................................................................................................................................28

3.4.2.1 Transmit Holding Register (THR) .................................................................................... 29

3.4.2.2 Transmitter Operation in non-FIFO mode ..................................................................... 29

3.4.2.3 Transmitter Operation in FIFO mode............................................................................. 29

3.4.2.4 Auto RS485 Operation ................................................................................................... 29

3.4.3 Baud Rate Generator Divisors (DLM, DLL and DLD) ....................................................................29

3.4.3.1 DLM[7:0], DLL[7:0] and DLD[3:0] ................................................................................... 30

Table 3.9 Typical Data Rates with Internal 125MHz Clock at 16X Sampling ............................... 31

Summary of Contents for AcroPack AP522

Page 1: ...SER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2019 Acromag Inc Printed in the USA Data and specifications ar...

Page 2: ...Figure 1 3 AP522 Block Diagram 6 1 3 1 Ordering Information 6 Table 1 1 Ordering Options 6 1 3 2 Key Features 6 1 3 3 Key Features PCIe Interface 7 1 4 Signal Interface Products 7 1 5 Software Suppor...

Page 3: ...ble 3 6 Timer Control Register 22 3 2 2 3 Timer Operation 22 3 2 3 8XMODE 7 0 default 0x00 23 3 2 4 4XMODE 15 8 default 0x00 24 3 2 5 RESET 23 16 default 0x00 24 3 2 6 SLEEP 31 24 default 0x00 24 3 2...

Page 4: ...gister 39 3 4 9 Line Status Register LSR Read Only 40 Table 3 17 Line Status Register 40 3 4 10 Modem Status Register MSR Read Only 41 Table 3 18 Modem Status Register 42 3 4 11 Modem Status Register...

Page 5: ...s 50 5 3 Environmental Considerations 50 5 3 1 Operating Temperature 50 5 3 2 Other Environmental Requirements 51 5 3 2 1 Relative Humidity 51 5 3 2 2 Isolation 51 5 3 3 Vibration and Shock Standards...

Page 6: ...p current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag 1 2 1 Trademark Trade Name and Copyright...

Page 7: ...Ports 8 Field I O Connector 1 3 1 Ordering Information The AcroPack ordering options are given in the following table Table 1 1 Ordering Options Model Number Type of Serial Ports Operational Temperat...

Page 8: ...I O cable is recommended 1 5 Software Support The AcroPack series products require support drivers specific to your operating system Supported operating systems include Linux Windows and VxWorks Wind...

Page 9: ...implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag AcroPack modules 1 6 References The following resources regarding AcroPack mo...

Page 10: ...c or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2 1 Unp...

Page 11: ...ltering In a conduction cooled assembly adequate thermal conduction must be provided to prevent a temperature rise above the maximum operating temperature 2 3 Board Configuration Power should be remov...

Page 12: ...O 3 3 2 2 TXD _A 5 Field I O 4 4 27 36 TXD _A 8 RSVD ISOL 7 RSVD ISOL 10 Field I O 5 5 3 3 RXD _A 9 Field I O 6 6 28 37 28 RXD _A 12 RSVD ISOL 11 RSVD ISOL 14 Field I O 7 7 4 4 TXD _B 13 Field I O 8...

Page 13: ...I O 21 21 11 11 GND 41 Field I O 22 22 36 45 GND 44 RSVD ISOL 43 RSVD ISOL 46 Field I O 23 23 12 12 TXD _E 45 Field I O 24 24 37 46 TXD _E 48 RSVD ISOL 47 RSVD ISOL 50 Field I O 25 25 13 13 RXD _E 49...

Page 14: ...I O 38 38 44 53 TXD _H 76 RSVD ISOL 75 RSVD ISOL 78 Field I O 39 39 20 20 RXD _H 77 Field I O 40 40 45 54 RXD _H 80 RSVD ISOL 79 RSVD ISOL 82 Field I O 41 41 21 21 GND 81 Field I O 42 42 46 55 GND 84...

Page 15: ...Connector The AP module logic edge connector interfaces to the mating connector on the carrier board The pin assignments of this connector are standard for all AP modules according to the PCI Express...

Page 16: ...or more information Note 3 5 12 and 12 Volt power supplies have been assigned to pins that are reserved in the mini PCIe specification Use of fuses on these power supplies along with new Present signa...

Page 17: ...uter s system configuration software scans the PCIe bus to determine what PCIe devices are present The software also determines the configuration requirements of the PCIe card The system software acce...

Page 18: ...ory BAR0 to access UART and device configuration registers Only 8K is used as the upper 8K is for a second slave UART connected to the master does not exist on the AP522 module 3 2 UART and Device Con...

Page 19: ...eserved 0x0100 0x01FF UART 0 FIFOs Read only 256 bytes of RX FIFO data 0x0100 0x01FF UART 0 FIFOs Write only 256 bytes of TX FIFO data 0x0200 0x03FF UART 0 Read FIFO with errors Read only 256 bytes of...

Page 20: ...egisters at address offset 0x088 0x08B 0X088 8XMODE Read Write 0x00 0x089 4XMODE Read Write 0x00 0x08A RESET Write only Self clear bits after executing Reset 0x00 0x08B SLEEP Read Write Sleep mode 0x0...

Page 21: ...ic 1 is an indication that the corresponding channel has called for service The interrupt bit clears after reading the appropriate register of the interrupting channel register see Interrupt Clearing...

Page 22: ...hat is in the UART channel register set Modem Status Register interrupt clears after reading the MSR register that is in the UART channel register set Xoff Xon delta and special character detect inter...

Page 23: ...r interrupt is enabled and there is a pending Timer interrupt It returns a value of 0x00 at all other times The default settings of the Timer upon power up a hardware reset or upon the issue of a Time...

Page 24: ...tput will stay HIGH until it reaches half of the terminal count N P clocks and toggle LOW and stay LOW for a similar amount of time Q clocks The above step will keep repeating until the Timer is stopp...

Page 25: ...to reset the UART s when there is a need The RESET register is accessible from the Device Configuration Registers in all UART channels but the UART channel can only control the bit for that channel Fo...

Page 26: ...us write to all 8 UARTs configuration register or individually This is very useful for device initialization in the power up and reset routines Table 3 7 REGB Register REGB 23 19 Not Used REGB 18 Glob...

Page 27: ...The software driver must separately read the LSR content for the associated error flags before reading the data byte 3 3 1 FIFO Data Loading and Unloading in 32 bit Format The XR17V358 supports 32 bi...

Page 28: ...in 8 Bit Format The THR and RHR for each channel 0 to 7 are located sequentially at address 0x0000 0x0400 0x0800 0x0C00 0x1000 0x1400 0x1800 and 0x1C00 Transmit data byte is loaded to the THR when wri...

Page 29: ...the middle of each data bit On the falling edge of a start or false start bit an internal receiver counter starts counting at the 16X 8X or 4X clock rate After 8 or 4 or 2 clocks the start bit period...

Page 30: ...tion control enabled FCTR bit 5 1 the source of the transmit empty interrupt changes to TSR empty instead of THR empty This is to ensure the RTS output is not changed until the last stop bit of the la...

Page 31: ...lity for selecting the operating data rate Table 3 5 shows the divisor for some standard and non standard data rates when using the internal 125 MHz clock at 16X clock rate If the pre scaler is used M...

Page 32: ...3 10 DLD Register 7 4 DLD BIT INTERRUPT ACTION 4 Not Used 5 Multi drop Mode 0 Normal mode 1 Enable Multi drop mode 6 XON XOFF Parity Check 0 XON XOFF characters are valid flow control characters even...

Page 33: ...be used in the polled mode by selecting respective transmit or receive control bit s A LSR BIT 0 indicates there is data in RHR non FIFO mode or RX FIFO FIFO mode B LSR BIT 1 indicates an overrun err...

Page 34: ...or Framing Error Parity Error or detection of a break character will result in an LSR interrupt An interrupt will be issued immediately after receiving a character with an error and again when the cha...

Page 35: ...s bit 0 5 for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupts 3 4 5 1 Interrupt Generation LSR is by any of the LSR bits 4 1 See IER bit 2 descr...

Page 36: ...FIFO Control Register is set to 1 A power up or system reset sets ISR bit 0 to logic 1 and bits 1 to 7 to logic 0 3 4 6 FIFO Control Register FCR Write Only This write only register is used to enable...

Page 37: ...did not get filled over the trigger level on last reload Refer to Table 3 10 for selections The FCTR 7 6 are associated with these 2 bits 7 6 Receive FIFO Trigger Select These two bits set the trigge...

Page 38: ...0 16C854 16C864 3 4 7 Line Control Register LCR Read Write The Line Control Register is used to specify the asynchronous data communication format The word length the number of stop bits and the parit...

Page 39: ...break is enabled the serial output line TxD is forced to the space state low This bit acts only on the serial output and does not affect transmitter logic For example if the following sequence is use...

Page 40: ...l Register MCR Bit FUNCTION PROGRAMMING 0 Data Terminal Ready Output Signal DTR 0 DTR Not Asserted Inactive 1 DTR Asserted Active 1 Ready to Send Output Signal RTS 0 RTS Not Asserted Inactive 1 RTS As...

Page 41: ...default 1 Indicates that data in the RHR is not being read before the next character is transferred into the RHR overwriting the previous character In the FIFO mode it is set after the FIFO is filled...

Page 42: ...ransmit FIFO to the transmit shift register 6 Transmitter Empty 0 Not Empty 1 Transmitter Empty set when both the transmit FIFO or THR in non FIFO mode and the Transmit Shift Register TSR are both emp...

Page 43: ...cleared on the trailing edge of the read instead of being set again 3 4 11 Modem Status Register MSR Write Only The upper four bits 7 4 of this register set the delay in number of bits time for the a...

Page 44: ...X data is ignored Xon xoff flow control characters are detected and acted upon 1 Transmitter Disable Modes This bit is only applicable when MSR 3 1 0 No Xon Xoff software flow control characters will...

Page 45: ...it the next character will be received normally It is recommended that the receiver be idle when resetting this bit to a logic 0 If the receiver is not idle RX pin is toggling at the time of setting t...

Page 46: ...ol Hysteresis Select Not supported 4 Not Used N A 5 Auto RS485 Enable Must be a logic 1 on the AP522 7 6 Tx and Rx FIFO Trigger Table Select 00 Table A 01 Table B 10 Table C 11 Table D refer to Table...

Page 47: ...R bits 4 5 MCR bits 5 7 This feature prevents existing software from altering or overwriting the enhanced functions 1 Enables the enhanced functions Allows the IER bits 4 7 ISR bits 4 5 FCR bits 4 5 a...

Page 48: ...can take advantage of the FIFO level byte counter for faster data unloading from the receiver FIFO which reduces CPU bandwidth requirements 3 4 18 Receive FIFO Trigger Level Write Only An 8 bit value...

Page 49: ...f the last transmitted control character was a Xoff character or characters Xoff1 Xoff2 this bit will be set to a logic 1 This bit will clear after the read 3 Transmit XON Indicator If the last transm...

Page 50: ...Procedure CAUTION POWER MUST BE TURNED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the do...

Page 51: ...lication with an AcroPack module will require purchase of the Heatsink AP CC 01 Table 5 1 Power Requirements Summarized below are the expected current draws for the specified power supply voltages Pow...

Page 52: ...ine 50G 3mS half sine 18 shocks at 6 orientations for both test levels 5 3 4 EMC Directives The AcroPack module is designed to comply with EMC Directive 2004 108 EC Immunity per EN 61000 6 2 Electrost...

Page 53: ...295 0310 52 http www acromag com 52 www acromag com 5 5 PCIe Bus Specifications Compatibility Conforms to PCI Express Base Specification Revision 2 0 Line Speed Gen1 2 5Gbps Lane Operation 1 Lane 16K...

Page 54: ...248 295 0310 53 http www acromag com 53 www acromag com Appendix A AP CC 01 Heatsink Kit Installation This example will show how to install the AP CC 01 Heatsink kit with an APCe7020 carrier AP CC 01...

Page 55: ...ER S MANUAL Acromag Inc Tel 248 295 0310 54 http www acromag com 54 www acromag com 1 Install two standoffs and secure with two screws 2 Install the AcroPack module 3 Install the Heatsink and secure w...

Page 56: ...P522 ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 55 http www acromag com 55 www acromag com 4 AP CC 01 Installation is complete Note Make sure the thermal pad is making contact with the UART I...

Page 57: ...of whose contents are lost when power is removed Yes No Type SRAM SDRAM etc UART Internal Registers FIFOs SRAM Size 8k bytes User Modifiable Yes No Function UART Communication Process to Sanitize Pow...

Page 58: ...y The revision history for this document is summarized in the table below Release Date DD MMM YYYY Version EGR DOC Description of Revision 28 JAN 2019 A LMP ARP Initial Release 11 JUL 2019 B ENZ ARP U...

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