AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 32 - http://www.acromag.com
- 32 -
www.acromag.com
A. The receive data available interrupts are issued to the host when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is
reached. Both the ISR register status bit and the interrupt will be cleared
when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR bit [0]) is set as soon as a character is
transferred from the shift register to the receive FIFO. It is reset when the
FIFO is empty.
3.4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0]
enables the XR17V358 in the FIFO polled mode of operation. Since the
receiver and transmitter have separate bits in the LSR either can be used in
the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR (non-FIFO mode) or RX FIFO (FIFO
mode).
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO
may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the
data byte in RHR, if any.
D. LSR BIT-5 indicates THR (non-FIFO mode) or TX FIFO (FIFO mode) is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO
Table 3.11 Interrupt Enable
Register
IER BIT
INTERRUPT ACTION
0
RX Interrupt Enable:
0 = Disable receive data ready interrupt (default).
1 = Enable receive data ready interrupt.
In non-FIFO mode an interrupt will be issued when RHR
has a data character. In FIFO mode an interrupt will be
issued when the FIFO has reached the programmed trigger
level and is cleared when the FIFO drops below the trigger
level. Note that the receive FIFO must also be enabled via
bit-0 of the FCR in FIFO mode.
1
TX Ready Interrupt Enable:
0 = Disable transmit ready interrupt (default).
