AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
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integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
Table 3.9 Typical Data Rates with
Internal 125MHz Clock at 16X
Sampling
Required
Output
Data Rate
Divisor for
16X Clock
(decimal)
Divisor
Obtainable in
XR17V358
DLM
Program
Value
(HEX)
DLL
Program
Value
(HEX)
DLD
Program
Value
(HEX)
Data
Error
Rate
(%)
9600
813.80
813 12/16
03
2D
D
0
19200
406.90
406 14/16
01
96
E
0.01
38400
203.45
203 7/16
00
CB
7
0.01
57600
135.63
135 10/16
00
87
A
0.01
115200
67.82
67 13/16
00
43
D
0.01
Note that there is a more extensive list of possible data rates in the Exar
datasheet.
3.4.3.2 DLD[7:4]
Table 3.10 DLD Register[7:4
]
DLD BIT
INTERRUPT ACTION
4
Not Used.
5
Multi-drop Mode:
0 = Normal mode.
1 = Enable Multi-drop mode.
6
XON/XOFF Parity Check:
0 = XON/XOFF characters are valid flow control characters
even if they have parity errors.
1 = XON/XOFF characters are not valid flow control
characters if they have parity errors.
7
Not Used.
3.4.4 Interrupt Enable Register (IER)
–
Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data
ready, transmit empty, line status and modem status registers. These
interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
3.4.4.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR bit [0] = logic 1) and receive interrupts (IER bit [0]
= logic 1) are enabled, the RHR interrupts (see ISR bits [4:3]) status will reflect
the following:
