AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 24 - http://www.acromag.com
- 24 -
www.acromag.com
8XMODE register is accessible from the Device Configuration Registers in all
UART channels but the UART channel can only control the bit for that
channel. For example, bit [0] is for channel 0 and can only be controlled by
channel 0. All other bits are read-only in channel 0. Logic 0 (default) selects
normal 16X sampling (with 4XMODE = 0x00) and logic one selects 8X
sampling rate. Transmit and receive data rates will double by selecting 8X. If
using the 4XMODE, the corresponding bit in this register should be logic 0.
3.2.4 4XMODE[15:8] (default 0x00)
Each bit selects 4X or 16X sampling rate for that UART channel. The
4XMODE register is accessible from the Device Configuration Registers in all
UART channels but the UART channel can only control the bit for that
channel. For example, bit [0] is channel 0 and can only be controlled by
channel 0. All other bits are read-only in channel 0. Logic 0 (default) selects
normal 16X sampling (with 8XMODE = 0x00) and logic one selects 4X
sampling rate. Transmit and receive data rates will quadruple by selecting
4X. If using the 8XMODE, the corresponding bit in this register should be
logic 0.
3.2.5 RESET[23:16] (default 0x00)
The 8-bit RESET register provides the software with the ability to reset the
UART(s) when there is a need. The RESET register is accessible from the
Device Configuration Registers in all UART channels but the UART channel
can only control the bit for that channel. For example, writing 0xFF to the
RESET register in channel 0 will only reset channel 0. Each bit is self-clearing
after it is written a logic 1 to perform a reset to that channel. All registers in
that channel will be reset to the default condition.
3.2.6 SLEEP[31:24] (default 0x00)
The 8-bit SLEEP register enables each UART separately to enter Sleep mode.
The SLEEP register is accessible from the Device Configuration Registers in
all UART channels but the UART channel can only control the bit for that
channel. For example, writing 0xFF to the SLEEP register in channel 0 will
only enable the sleep mode for channel 0. Sleep mode reduces power
consumption when the system needs to put the UART(s) to idle. The UART
enters sleep mode when the following conditions are satisfied after the
sleep mode is enabled (Logic 0 (default) is to disable and logic 1 is to enable
sleep mode):
•
Transmitter and Receiver are empty (LSR[6]=1, LSR[0]=0)
•
RX pin is idling at a HIGH in normal mode
The XR17V358 is awakened by any of the following events occurring at any
of the 8 UART channels:
•
A receive data start bit transition (HIGH to LOW in normal mode)
•
A data byte is loaded into the transmitter
A receive data start bit transition will not wake up the UART if the Multidrop
mode is disabled (DLD[6] = 0) and the receiver is disabled (MSR[2] = 1,
MSR[0] = 0).
