AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 29 - http://www.acromag.com
- 29 -
www.acromag.com
FIFO when the FIFO is enabled by FCR bit [0]. TSR shifts out every data bit
with the 16X or 8X internal clock. A bit time is 16 or 8 clock periods. The
transmitter sends the start bit followed by the number of data bits, inserts
the proper parity bit if enable, and adds the stop bit(s). The status of the THR
and TSR are reported in the Line Status Register (LSR bit [6:5]).
3.4.2.1 Transmit Holding Register (THR)
The transmit holding register is an 8-bit register providing a data interface to
the host processor. The host writes transmit data byte to the THR to be
converted into a serial data stream including start-bit, data bits, parity-bit
and stop-bit(s). The least-significant-bit (bit [0]) becomes first data bit to go
out. The THR is also the input register to the transmit FIFO of 256 bytes when
FIFO operation is enabled by FCR bit[0]. A THR empty interrupt can be
generated when it is enabled in IER bit [1].
3.4.2.2 Transmitter Operation in non-FIFO mode
The host loads transmit data to THR one character at a time. The THR empty
flag (LSR bit [5]) is set when the data byte is transferred to TSR. THR flag can
generate a transmit empty interrupt (ISR bit [1]) when it is enabled by IER bit
[1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit
[5]=1) the source of the transmit empty interrupt changes to TSR empty
instead of THR empty. This is to ensure the RTS# output is not changed until
the last stop bit of the last character is shifted out.
3.4.2.3 Transmitter Operation in FIFO mode
The host may fill the transmit FIFO with up to 256 bytes of transmit data. The
THR empty flag (LSR bit [5]) is set whenever the FIFO is empty. The THR
empty flag can generate a transmit empty interrupt (ISR bit [1]) when the
amount of data in the FIFO falls below its programmed trigger level (see
TXTRG register). The transmit empty interrupt is enabled by IER bit [1]. The
TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
3.4.2.4 Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the
transmitter when enabled by FCTR bit [5]. It de-asserts RTS# after a specified
delay indicated in MSR[7:4] following the last stop bit of the last character
that has been transmitted. This helps in turning around the transceiver to
receive the remote station’s response. The delay optimizes the time
needed
for the last transmission to reach the farthest station on a long cable network
before switching off the line driver. This delay prevents undesirable line
signal disturbance that causes signal degradation. It also changes the
transmitter empty interrupt to TSR empty instead of THR empty.
3.4.3 Baud Rate Generator Divisors (DLM, DLL and DLD)
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the
transmitter and receiver. The prescaler is controlled by a software bit in the
