Acromag AcroPack AP522, User Manual

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AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310 - 20 - http://www.acromag.com - 20 - www.acromag.com
Table 3.4 Device Configuration
Registers in DWORD Alignment
Address
Offset
Register BYTE 3
[31:24]
BYTE 2
[32:16]
BYTE 1
[15:8]
BYTE 0
[7:0]
0x0080 –
0x0083
INTERRUPT
(read only)
INT3 INT2 INT1 INT0
0x0084 –
0x0087
TIMER
(read/write)
TIMERMSB TIMERLSB Reserved TIMERCTL
0x0088 –
0x008B
ANCILLARY1
(read/write) SLEEP RESET 4XMODE 8XMODE
0x008C –
0x008F
ANCILLARY2
(read only)
Not used. REGB DVID DREV
0x0090 –
0x0093
MPIO1
(read/write)
Not Used. Not Used. Not
Used.
MPIOLVL
[7:0]
0x0094 –
0x0097
MPIO2
(read/write)
Not Used. MPIOLVL
[15:8]
Not
Used.
Not Used.
0x0098 –
0x009B
MPIO3
(read/write)
Reserved Not Used. Not
Used.
Not Used.
3.2.1 The Global Interrupt Registers – INT0, INT1, INT2 and INT3
The XR17V358 can support two different interrupt schemes with a 32-bit
wide register [INT3, INT2, INT1 and INT0]. The first scheme uses INT0 (bits
[7:0]) along with the Interrupt Status Register (ISR) of the individual UART
channels. Each bit gives an indication of the channel that has requested for
service. Bit [0] represents channel 0 and bit [7] indicates channel 7. Logic 1 is
an indication that the corresponding channel has called for service. The
interrupt bit clears after reading the appropriate register of the interrupting
channel register, see Interrupt Clearing section.
The second interrupt scheme uses INT3 – INT1 to provide details about the
source of the interrupts for each UART channel. Interrupts are encoded into
a 3-bit code where bits [10:8] represent channel 0 and bits [31:29] represent
channel 7, respectively. Using this scheme, the highest pending interrupt for
all 8 channels are available with a single DWORD read operation without
having to read the ISR register of the individual UART channels. The 3-bit
encoding and their priority order are shown in the table below. If there is a
global interrupt such as the wake-up interrupt, timer/counter interrupt or
MPIO interrupt, then they would be reported in the 3-bit code for channel 0
in INT1 bits [10:8]. However, since the UART interrupts have a higher
priority, all UART channel 0 interrupts must first be cleared before any of
the global interrupts can be reported in INT1 bits [10:8].
All bits start up zero. A special interrupt condition is generated by the
XR17V358 upon awakening from sleep after all eight channels were put to
sleep mode earlier. This wake-up interrupt is cleared by a read to the INT0
register.