AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 42 - http://www.acromag.com
- 42 -
www.acromag.com
Table 3.18 Modem Status
Register
MSR
BIT
FUNCTION
0
CTS
–
NOT SUPPORTED
1
DSR - NOT SUPPORTED
2
RI - NOT SUPPORTED
3
CD - NOT SUPPORTED
4
CTS
–
NOT SUPPORTED
5
DSR - NOT SUPPORTED
6
RI - NOT SUPPORTED
7
CD - NOT SUPPORTED
Note that reading MSR clears the delta-modem status indication but has no
effect on the status bit. For both the LSR & MSR, the setting of the status bits
during a status register read operation is inhibited (the status bit will not be
set until the trailing edge of the read). However, if the same status condition
occurs during a read operation, that status bit is cleared on the trailing edge
of the read instead of being set again.
3.4.11 Modem Status Register (MSR)
–
Write Only
The upper four bits [7:4] of this register set the delay in number of bits time
for the auto RS-485 turnaround from transmit to receive.
MSR [7:4]: Auto RS485 Turn-Around Delay (requires EFR bit [4]=1)
When Auto RS485 feature is enabled (FCTR bit [5]=1) and RTS# output is
connected to the enable input of a RS-485 transceiver. These 4 bits select
from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS#
output. This delay is very useful in long-cable networks. The table below
shows the selection. The bits are enabled by EFR bit-4.
Table 3.19 Auto RS485 Half-
Duplex Direction Control Delay
from Transmit to Receive
MSR[7:4]
DELAY IN BIT TIMES
0000
0
0001
1
0010
2
0011
3
0100
4
