AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 26 - http://www.acromag.com
- 26 -
www.acromag.com
3.3 Transmit and Receive Data
There are two methods to load transmit data and unload receive data from
each UART channel. First, there is a transmit data register and receive data
register for each UART channel as shown in Table 3.2 set to ease
programming. These registers support 8, 16,
24 and 32-bit wide format. In
the 32-bit format, it increases the data transfer rate on the PCI bus.
Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the Line
Status Register (LSR) content in the UART channel register is paired along
with the data byte. This operation further facilitates data unloading with the
error flags without having to read the LSR register separately. Furthermore,
the XR17V358 supports 32-bit read/write operation of up to 256 bytes of
data.
The second method
is through each UART channel’s transmit holding register
(THR) and receive holding register (RHR). The THR and RHR registers are
16550 compatible so their access is limited to 8-bit format. The software
driver must separately read the LSR content for the associated error flags
before reading the data byte.
3.3.1 FIFO Data Loading and Unloading in 32-bit Format
The XR17V358 supports 32-bit Read and 32-bit Write transactions anywhere
in the mapped memory region (except reserved areas). In addition, to utilize
this feature fully, the device provides a separate memory location (apart
from the individual channel’s register set)
where the RX and the TX FIFO can
be read from/written to, as shown in Table 3.2. The following is an extract
from the table showing the memory locations that support 32-bit
transactions:
Channel N: (for channels 0 through 7) where M = 4N + 1.
RX FIFO: 0xM00
–
0xMFF (256 bytes)
TX FIFO: 0xM00
–
0xMFF (256 bytes)
RX FIFO + status: 0x(M+1)00
–
0x(M+2)FF (256 bytes data+256 bytes status)
For example, the locations for channel 2 are:
RX FIFO: 0x0900
–
0x09FF (256 bytes)
TX FIFO: 0x0900
–
0x09FF (256 bytes)
RX FIFO + status: 0x0A00
–
0x0BFF (256 bytes data+256 bytes status)
Normal Rx/Tx FIFO Data Unloading/Loading at Locations 0x0100, 0x0500,
0x0900, 0x0D00, 0x1100, 0x1500, 0x1900 and 0x1D00:
The RX FIFO data can be read out 32-bits at a time at memory locations
0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel 2), 0x0D00 (channel
3), 0x1100 (channel 4), 0x1500 (channel 5), 0x1900 (channel 6), 0x1D00
(channel 7). This operation is 4 times faster than reading the data in 256
