AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 27 - http://www.acromag.com
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www.acromag.com
separate 8-bit memory reads of RHR register (0x0000 for channel 0, 0x0400
for channel 1, 0x0800 for channel 2, 0x0C00 for channel 3, 0x1000 for
channel 4, 0x1400 for channel 5, 0x1800 for channel 6 and 0x1C00 for
channel 7).
The TX FIFO data can be loaded 32-bit (4 bytes) at a time at memory locations
0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel 2), 0x0D00 (channel
3), 0x1100 (channel 4), 0x1500 (channel 5), 0x1900 (channel 6) and 0x1D00
(channel 7).
Special Rx FIFO Data Unloading at Locations 0x0200, 0x0600, 0x0A00,
0x0E00, 0x1200, 0x1600, 0x1A00 and 0x1E00:
The XR17V358 also provides the same RX FIFO data along with the LSR status
information of each byte side-by-side, at locations 0x0200 (channel 0),
0x0600 (channel 1), 0x0A00 (channel 2) 0x0E00 (channel 3), 0x1200 (channel
4), 0x1600 (channel 5), 0x1A00 (channel 6) and 0x1E00 (channel 7). The
Status and Data bytes must be read in 16 or 32-bit format to maintain data
integrity.
3.3.2 FIFO Data Loading/Unloading Through the UART Channel Registers, THR and RHR, in 8-Bit Format
The THR and RHR for each channel 0 to 7 are located sequentially at address
0x0000, 0x0400, 0x0800, 0x0C00, 0x1000, 0x1400, 0x1800 and 0x1C00.
Transmit data byte is loaded to the THR when writing to that address and
receive data is unloaded from the RHR register when reading that address.
Both THR and RHR registers are 16C550 compatible in 8-bit format, so each
bus operation can only write or read in bytes.
3.4 UART Channel Configuration Registers
There are 8 UARTs channel [7:0] in the XR17V358. Each has its own 256-byte
of transmit and receive FIFO, a set of 16550 compatible control and status
registers, and a baud rate generator for individual channel data rate setting.
Eight additional registers per UART were added for the EXAR enhanced
features.
Address lines A0 to A3 select the 16 registers in each channel. The first 8
registers are 16550 compatible with EXAR enhanced feature registers located
on the upper 8 addresses.
Table 3.8 UART Channel
Configuration Registers
A[3:0]
Registers
Read/Write Comments
16550 COMPATIBLE
0 0 0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7]=0
0 0 0 0
DLL - Divisor LSB
Read/Write
LCR[7]=1
0 0 0 1
IER - Interrupt Enable Register
Read/Write
LCR[7]=0
0 0 0 1
DLM - Divisor MSB
Read/Write
LCR[7]=1
