AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 28 - http://www.acromag.com
- 28 -
www.acromag.com
0 0 1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR[7]=0
0 0 1 0
DLD - Divisor Fractional
Read/Write
LCR[7]=1
0 0 1 1
LCR - Line Control Register
Read/Write
0 1 0 0
MCR - Modem Control Register
Read/Write
0 1 0 1
LSR - Line Status Register
Read-only
0 1 1 0
MSR - Modem Status Register
-Auto RS485 Delay
Read-only
Write-only
EFR bit-4=1
0 1 1 1
SPR- Scratch Pad Register
Read/Write
ENHANCED REGISTER
1 0 0 0
FCTR - Feature Control Register
Read/Write
1 0 0 1
EFR - Enhanced Function Register Read/Write
1 0 1 0
TXCNT - Tx FIFO Level Counter
TXTRG - Tx FIFO Trigger Level
Read-only
Write-only
1 0 1 1
RXCNT- Rx FIFO Level Counter
RXTRG
–
Rx FIFO Trigger Level
Read-only
Write-only
1 1 0 0
Xoff-1 - Xoff Character 1
Xchar
Write-only
Read-only
Xon,Xoff
Rcvd. Flags
1 1 0 1
Xoff-2 - Xoff Character 2
Write-only
1 1 1 0
Xon-1 - Xon Character 1
Write-only
1 1 1 1
Xon-2 - Xon Character 2
Write-only
3.4.1 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and
Receive Holding Register (RHR). The RSR uses the 16X, 8X or 4X clock for
timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X, 8X or 4X clock rate. After
8 or 4 or 2 clocks the start bit period should be at the center of the start bit.
At this time the start bit is sampled and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling
a false character. The rest of the data bits and stop bits are sampled and
validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits [4:1]. Upon unloading the
receive data byte from RHR, the receive FIFO pointer is bumped and the error
flags are immediately updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready interrupt upon receiving a
character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out function
when receive data does not reach the receive FIFO trigger level. This time-out
delay is 4 word lengths as defined by LCR bits [1:0] plus 12 bits time. The RHR
interrupt is enabled by IER bit [0].
3.4.2 Transmitter
The transmitter section comprises of a 256 byte FIFO, a byte-wide Transmit
Holding Register (THR) and an 8-bit Transmit Shift Register (TSR). THR
receives a data byte from the host (non-FIFO mode) or a data byte from the
