AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 17 - http://www.acromag.com
- 17 -
www.acromag.com
Table 3.1 PCI Configuration
Registers
Address
Offset
D31 D24 D23 D16 D15 D8 D7 D0
0x00
Device ID
0x0358 AP522
Vendor ID
0x13A8
0x04
Status
Command
0x08
Class Code=0x070002
Rev ID=
Current REV
0x0C
BIST
Header
Latency
Cache
0x10
Memory Base Address for Memory Accesses
to PCIe interrupt and I/O registers
16K Space
(BAR0)
0x14-
0x28
Not Used
0x2C
Subsystem ID
0x0000
Subsystem Vendor ID
0x0000
0x30
Not Used
0x34-
0x38
Reserved
0x3C
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 16K byte block of memory (BAR0), to access UART
and device configuration registers. Only 8K is used, as the upper 8K is for a
second 'slave' UART connected to the master does not exist on the AP522
module.
3.2 UART and Device Configuration Registers
The Device Configuration Registers and the eight individual UART
Configuration Registers occupy 8K of PCI bus memory address space. These
registers are offset from the BAR0 address as identified in the PCI
Configuration Registers in the previous section.
Each UART Configuration Register occupies 1K byte of memory space that
include the 16550 compatible registers.
The Device Configuration Registers are accessible from all UART channels,
however not all bits can be controlled by all channels. The control of the
8XMODE, 4XMODE, RESET, and SLEEP bits are only available for that
particular channel.
