AP522 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 30 - http://www.acromag.com
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www.acromag.com
MCR register. The MCR register bit [7] sets the prescaler to divide the internal
125 MHz clock by 1 or 4. The output of the prescaler clocks to the BRG. The
BRG further divides this clock by a programmable divisor between 1 and (2
16
-
0.0625) in increments of 0.0625 (1/16) to obtain a 16X, 8X or 4X sampling
clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling.
3.4.3.1 DLM[7:0], DLL[7:0] and DLD[3:0]
The Baud Rate Generator (BRG) generates the data rate for the transmitter
and receiver. The rate is programmed through registers DLM, DLL and DLD
which are only accessible when LCR bit [7] is set to logic 1.
The BRG divisor (DLL, DLM and DLD registers) defaults to 1 (DLL = 0x01, DLM
= 0x00, DLD = 0x00). The DLL and DLM registers provide the integer part of
the divisor and the DLD register provides the fractional part of the divisor.
Only the four lower bits of the DLD are implemented and they are used to
select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111).
Programming the Baud Rate Generator Registers DLL, DLM and DLD provides
the capability for selecting the operating data rate. Table 3.5 shows the
divisor for some standard and non-standard data rates when using the
internal 125 MHz clock at 16X clock rate. If the pre-scaler is used (MCR bit [7]
= 1), the output data rate will be 4 times less than that shown in Table 3.5. At
8X sampling rate, these data rates would double. At 4X sampling rate, these
data rates would quadruple. Also, when using 8X or 4X sampling mode, note
that the bit-time will have a jitter (+/- 1/16) whenever the DLD is an odd
number. For data rates not listed in Table 3.5, the divisor value can be
calculated with the following equation(s):
Calculated Divisor (decimal) = (125 MHz clock frequency / prescaler) /
(desired data rate x 16),
WHEN 8XMODE = 0 AND 4XMODE = 0
Calculated Divisor (decimal) = (125 MHz clock frequency / prescaler / (desired
data rate x 8),
WHEN 8XMODE = 1 AND 4XMODE = 0
Calculated Divisor (decimal) = (125 MHz clock frequency / prescaler / (desired
data rate x 4),
WHEN 8XMODE = 0 AND 4XMODE = 1
The closest actual divisor that is obtainable in the XR17V358 can be
calculated using the following formula:
Actual Divisor (decimal) = ROUND( (Calculated Divisor - TRUNC (Calculated
Divisor) )*16)/16 + TRUNC (Calculated Divisor),
DLM = TRUNC (Actual Divisor in hex) >> 8
DLL = TRUNC (Actual Divisor in hex) & 0xFF
DLD = ROUND ( (Calculated Divisor - TRUNC (Calculated Divisor) )*16)
In the formulas above, please note that: TRUNC (N) = Integer Part of N. For
example, TRUNC (5.6) = 5. ROUND (N) = N rounded towards the closest
