234
MC96F6432S
ABOV Semiconductor Co., Ltd.
12.5 Release Operation of STOP Mode
After STOP mode is released, the operation begins according to content of related interrupt register just before STOP
mode start (Figure 12.3).If the global interrupt Enable Flag (IE.EA)is set to `1`, the STOP mode isreleased by the
interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine. Even if the
IE.EA bit is cleared to
‘0’, the STOP mode is released by the interrupt of which the interrupt enable flag is set to ‘1’.
Figure 12.3
STOP Mode Release Flow
SET PCON[7:0]
SET IEx.b
STOP Mode
IEx.b==1 ?
Interrupt Request
STOP Mode Release
Y
Interrupt Service
Routine
Next Instruction
N
Corresponding Interrupt
Enable Bit(IE, IE1, IE2, IE3)
Summary of Contents for MC96F6432S Series
Page 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...
Page 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...
Page 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...
Page 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...
Page 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...
