201
MC96F6432S
ABOV Semiconductor Co., Ltd.
11.12.20.1
USIn I2C Master Transmitter
To operate I2C in master transmitter, follow the recommended steps below.
1.
Enable I2C by setting USInMS[1:0]bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to
the peripheral.
2.
Load SLAn+W into the USInDR where SLAn is address of slave device and W is transfer direction from the
viewpoint of the master. For master transmitter, W is
‘0’. Note that USInDR is used for both address and data.
3.
Configure baud rate by writing desired value to both USInSCLR and USInSCHR for the Low and High period
of SCLn line.
4.
Configure the USInSDHR to decide when SDAn changes value from falling edge of SCLn. If SDAn should
change in the middle of SCLn LOW period, load half the value of USInSCLR to the USInSDHR.
5.
Set the STARTCn bit in USInCR4. This transmits a START condition. And also configure how to handle
interrupt and ACK signal. When the STARTCn bit is set, 8-bit data in USInDR is transmitted out according to
the baud-rate.
6.
This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit
transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged
or not in the 9
th
high period of SCLn. If the master gains bus mastership, I2C generates GCALL interrupt
regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration
process, the MLOSTn bit in USInST2 is set, and I2C waits in idle state or can be operate as an addressed
slave.To operate as a slave when the MLOSTn bit in USInST2 is set, the ACKnEN bit in USInCR4 must be
set and the received 7-bit address must equal to the USInSLA[6:0] bits in USInSAR. In this case I2C
operates as a slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the
SCLn LOW. This is because to decide whether I2C continues serial transfer or stops communication. The
following steps continue assuming that I2C does not lose mastership during first data transfer.
I2C (Master) can choose one of the following cases regardless of the reception of ACK signal from slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data
from master. In this case, load data to transmit to USInDR.
2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOPCn bit in
USInCR4.
3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLAn+R/W
into the USInDR and set STARTCn bit in USInCR4.
After doing one of the actions above, clear to
“0b” all interrupt source bits in USInST2 to release SCLn line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to
step 6 after transmitting the data in USInDR and if transfer direction bit is
‘1’ go to master receiver section.
7.
1-Byte of data is being transmitted. During data transfer, bus arbitration continues.
Summary of Contents for MC96F6432S Series
Page 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...
Page 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...
Page 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...
Page 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...
Page 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...