Abov MC96F6432S Series User Manual Download

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MC96F6432S

ABOV Semiconductor Co., Ltd.

Figure 7.21

STOP (IDD5) Current

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Summary of Contents for MC96F6432S Series

Page 1: ...Detect Reset Internal 16MHz RC Oscillator 1 5 TA 0 50 C Watchdog Timer RC Oscillator 5kHz Peripheral Features 12 bit Analog to Digital Converter 16inputs USI USART SPI I2C 2sets LCD Driver 21segments...

Page 2: ...D Converter 1 5 2015 05 11 Add a chapter 17 3 ESD Test Method 1 6 2015 12 09 Add package of 32 LQFP MC96F6332SL 1 7 2016 04 06 Add Flash Data Retention Time in Chapter 7 15 Internal Flash Rom Charact...

Page 3: ...nterval timer watchdog timer 8 16 bit timer counter 16 bit PPG output 8 bit PWM output 10 bit PWM output watch timer buzzer driving port SPI USI 12 bit A D converter LCD driver on chip POR LVR LVI on...

Page 4: ...nternal Resistors Selectable 1 2 1 3 1 4 1 5 1 6 and 1 8 duty selectable Resistor Bias and 16 step contrast control Power On Reset Reset release level 1 4V Low Voltage Reset 14 levels detect 1 60 2 00...

Page 5: ...nitoring etc The OCD debugger program works on Microsoft Windows NT 2000 XP Vista 32 bit operating system If you want to see more details please refer to OCD debugger manual You can download debugger...

Page 6: ...6 MC96F6432S ABOV Semiconductor Co Ltd 1 3 3 Programmer Single programmer E PGM It programs MCU device directly Figure 1 2 E PGM Single writer...

Page 7: ...or Co Ltd Gang programmer E GANG4 and E GANG6 It can run PC controlled mode It can run standalone without PC control too USB interface is supported Easy to connect to the handler Figure 1 3 E GANG4 an...

Page 8: ...ignal lines are ready at the PCB of application board is designed 1 4 2 1 Circuit Design Guide At the FLASH programming the programming tool needs 4 signal lines that areDSCL DSDA VDD and VSS When you...

Page 9: ...ed to pin DSCL and DSDA And it will cause some damages to the application circuits connected to DSCL or DSDA port if the application circuit is designed as high speed response such as relay control ci...

Page 10: ...68kHz Crystal OSC LCD driver 21 segments Buzzer 1 channel 8 bit UART 2 channels 8 bit SPI 3 channels 8 bit I2C 2 channels 8 bit CORE M8051 General purpose I O 9 ports normal I O 33 ports LCD shared I...

Page 11: ...NT6 SS2 P07 SEG22 AN5 EINT5 PWM4CB P15 SEG19 AN8 MISO2 P16 SEG20 AN7 EINT7 SCK2 P13 SEG17 AN10 EC1 BUZO P14 SEG18 AN9 MOSI2 P06 SEG23 AN4 EINT4 PWM4CA P25 SEG8 P24 SEG9 P23 SEG10 P22 SEG11 SS1 P21 SEG...

Page 12: ...CA P22 SEG11 SS1 P21 SEG12 AN15 SCK1 P20 SEG13 AN14 TXD1 SDA1 MOSI1 P10 SEG14 AN13 RXD1 SCL1 MISO1 P27 SEG6 P26 SEG7 P31 COM6 SEG4 P30 COM7 SEG5 P51 XIN P50 XOUT P02 AN0 AVREF EINT0 T4O PWM4AA P01 T3O...

Page 13: ...ed as a push pull output or an input with pull up resistor by software control when the 32 pin package is used Figure 3 3 MC96F6332SD 32SOP pin assignment 1 2 13 14 8 9 10 11 12 3 4 5 6 7 16 15 21 20...

Page 14: ...EF EINT0 T4O PWM4AA P21 SEG12 AN15 SCK1 P20 SEG13 AN14 TXD1 SDA1 MOSI1 VDD P05 SEG24 AN3 EINT3 PWM4BB P04 SEG25 AN2 EINT2 PWM4BA P07 SEG22 AN5 EINT5 PWM4CB P11 SEG15 AN12 EINT12 T2O PWM2O P12 SEG16 AN...

Page 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...

Page 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...

Page 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...

Page 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...

Page 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...

Page 20: ...SEG18 AN9 MOSI2 P15 SEG19 AN8 MISO2 P16 SEG20 AN7 EINT7 SCK2 P17 SEG21 AN6 EINT6 SS2 P20 I O Port 2 is a bit programmable I O port which can be configured as an input a push pull output or an open dr...

Page 21: ...put Input P12 SEG16 AN11 T1O PWM1O EINT12 I O External interrupt input and Timer 2 capture input Input P11 SEG15 AN12 T2O PWM2O T0O I O Timer 0 interval output Input P53 SXIN PWM0O T1O I O Timer 1 int...

Page 22: ...EINT6 TXD0 I O UART 0 data output Input P41 VLC2 SDA0 MOSI0 TXD1 I O UART 1 data output Input P20 SEG13 AN14 SDA1 MOSI1 RXD0 I O UART 0 data input Input P40 VLC3 SCL0 MISO0 RXD1 I O UART 1 data input...

Page 23: ...nal outputs Input P35 P34 COM2 COM3 SEG2 SEG5 P33 P30 COM4 COM7 SEG6 SEG10 P27 P23 SEG11 P22 SS1 SEG12 P21 SCK1 AN15 SEG13 P20 AN14 TXD1 SDA1 MOSI1 SEG14 P10 AN13 RXD1 SCL1 MISO1 SEG15 P11 AN12 EINT12...

Page 24: ...escription continue NOTE 1 The P14 P17 P23 P25 P34 P37 and P43 are not in the 32 pin package 2 The P13 P17 P22 P27 P34 P37 and P43 are not in the 28 pin package 3 The P55 RESETB pin is configured as o...

Page 25: ...VDD OPEN DRAIN REGISTER DATA REGISTER DIRECTION REGISTER MUX 0 1 MUX 1 0 CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or SUB FUNC DATA INPUT SUB FUNC DIRECTION SUB FUNC E...

Page 26: ...1 0 INTERRUPT ENABLE EXTERNAL INTERRUPT Q D CP r VDD FLAG CLEAR POLARITY REG MUX 1 0 DEBOUNCE ENABLE Q D CP r DEBOUNCE CLK CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or...

Page 27: ...beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond those in...

Page 28: ...AN AVREF 5 12V 2 uA ADC Operating Current IADC Enable VDD 5 12V 1 2 mA Disable 0 1 uA Table 7 3 A D Converter Characteristics NOTE 1 Zero offset error is the difference between 000000000000 and the co...

Page 29: ...steresis V 50 150 mV Minimum Pulse Width tLW 100 us LVR and LVI Current IBL Enable Both VDD 3V RUN Mode 14 0 24 0 uA Enable One of two 10 0 18 0 Disable Both VDD 3V 0 1 Table 7 5 LVR and LVI Character...

Page 30: ...CDCCR 00H Typx0 9 VDDx16 31 Typx1 1 V LCDCCR 01H VDDx16 30 LCDCCR 02H VDDx16 29 LCDCCR 03H VDDx16 28 LCDCCR 04H VDDx16 27 LCDCCR 05H VDDx16 26 LCDCCR 06H VDDx16 25 LCDCCR 07H VDDx16 24 LCDCCR 08H VDDx...

Page 31: ...dback resistor RX1 XIN VDD XOUT VSS TA 25 C VDD 5V 600 1200 2000 k RX2 SXIN VDD SXOUT VSS TA 25 C VDD 5V 2500 5000 10000 Table 7 9 DC Characteristics TA 40 C 85 C VDD 1 8V 5 5V VSS 0V fXIN 12MHz Param...

Page 32: ...5V 10 us Interrupt input high low width tIWH tIWL All interrupt VDD 5V 200 ns External Counter Input High Low Pulse Width tECWH tECWL ECn VDD 5V n 0 1 3 200 External Counter Transition Time tREC tFEC...

Page 33: ...Internal SCK source 70 Input Clock High Low Pulse Width External SCK source 70 First Output Clock Delay Time tFOD Internal External SCK source 100 Output Clock Delay Time tDS 50 Input Setup Time tDIS...

Page 34: ...put data valid tS2 590 ns Output data hold after clock rising edge tH1 tCPU 50 tCPU ns Input data hold after clock rising edge tH2 0 ns Serial port clock High Low level width tHIGH tLOW 470 tCPU x 8 9...

Page 35: ...tSCLL 4 7 1 3 Bus Free Time tBF 4 7 1 3 Start Condition Setup Time tSTSU 4 7 0 6 Start Condition Hold Time tSTHD 4 0 0 6 Stop Condition Setup Time tSPSU 4 0 0 6 Stop Condition Hold Time tSPHD 4 0 0 6...

Page 36: ...mer Active VDD NOTE tWAIT is the same as the selected bit overflow of BIT X 1 BIT Clock INT Request Execution of STOP Instruction Data Retention Stop Mode Normal Operating Mode 0 8VDD tWAIT VDDDR Figu...

Page 37: ...Frequency fPGM 0 4 MHz Endurance of Write Erase NFWE 100 000 times Flash Data Retention Time tRT 10 Years Table 7 16 Internal Flash Rom Characteristics NOTE 1 During a flash operation SCLK 1 0 of SCCR...

Page 38: ...2 MHz 2 7V 5 5V 0 4 10 0 3 0V 5 5V 0 4 12 0 Ceramic Oscillator Main oscillation frequency 1 8V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 10 0 3 0V 5 5V 0 4 12 0 External Clock XIN input frequency 1 8V 5 5V 0 4 4...

Page 39: ...llator Parameter Condition MIN TYP MAX Unit Crystal Sub oscillation frequency 1 8V 5 5V 32 32 768 38 kHz External Clock SXIN input frequency 32 100 kHz Table 7 19 Sub Clock Oscillator Characteristics...

Page 40: ...h and low width tXH tXL 42 1250 ns Table 7 20 Main Oscillation Stabilization Characteristics tXH tXL XIN 0 2VDD 0 8VDD 1 fXIN Figure 7 12 Clock Timing Measurement at XIN 7 20 Sub Oscillation Character...

Page 41: ...Semiconductor Co Ltd 7 21 Operating Voltage Range 1 8 0 4MHz 3 0 5 5 12 0MHz fXIN 0 4 to 12MHz Supply voltage V 4 2MHz 1 8 5 5 32 768kHz Supply voltage V fSUB 32 to 38kHz 10 0MHz 2 7 Figure 7 14 Opera...

Page 42: ...vely for noise immunity X tal SXOUT SXIN 32 768kHz The main and sub crystal should be within 1cm from the pins of MCU on the PCB layout 0 1uF VDD VCC The MCU power line VDD and VSS should be separated...

Page 43: ...mmended C2 47uF 25V more The R1 and C2 should be as close by the C3 as possible 3 The C3 capacitor is used for temperature compensation because an electrolytic capacitor becomes worse characteristics...

Page 44: ...rate properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical represents the me...

Page 45: ...Figure 7 19 SUB RUN IDD3 Current Figure 7 20 SUB IDLE IDD4 Current 0 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 2 7V 3 0V 3 3V 4 5V 5 0V 5 5V uA 40 25 85 0 00 5 00 10 00 15 00 20 00 25 00 30 00 2...

Page 46: ...46 MC96F6432S ABOV Semiconductor Co Ltd Figure 7 21 STOP IDD5 Current 0 00 0 50 1 00 1 50 2 00 2 50 3 00 3 50 4 00 4 50 5 00 2 7V 3 0V 3 3V 4 5V 5 0V 5 5V uA 40 25 85...

Page 47: ...f addressing up to 64Kbytes but this device has just 32Kbytes program memory space Figure 8 1shows the map of the lower part of the program memory After reset the CPU begins execution from location 00...

Page 48: ...48 MC96F6432S ABOV Semiconductor Co Ltd FFFFH 0000H 32Kbytes 7FFFH Figure 8 1 Program Memory NOTE 1 32Kbytes Including Interrupt Vector Region...

Page 49: ...cupying the same block of addresses 80H through FFH although they are physically separate entities The lower 128bytes of RAM are present in all 8051 devices as mapped in Figure 8 3 The lowest 32bytes...

Page 50: ...5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B...

Page 51: ...SFR This area has no relation with RAM FLASH It can be read and written to through SFR with 8 bit unit External RAM 768bytes Indirect Addressing LCD Display RAM 0000H 001AH 001BH 02FFH 107FH 1000H Ext...

Page 52: ...B8H IP P2IO T1CRL T1CRH T1ADRL T1ADRH T1BDRL T1BDRH 0B0H P5 P1IO T0CR T0CNT T0DR T0CDR SPICR SPIDR SPISR 0A8H IE IE1 IE2 IE3 P0PU P1PU P2PU P3PU 0A0H P4 P0IO EO P4PU EIPOL0L EIPOL0H EIFLAG1 EIPOL1 98H...

Page 53: ...0EH 07H 0FH 1078H 1070H 1068H 1060H 1058H 1050H 1048H 1040H 1038H 1030H 1028H 1020H 1018H 1010H T4DLYA T4DLYB T4DLYC T4DR T4CAPR T4CNT 1008H T4PPRL T4PPRH T4ADRL T4ADRH T4BDRL T4BDRH T4CDRL T4CDRH 10...

Page 54: ...0 0 0 0 8EH Watch Dog Timer Data Register WDTDR W 1 1 1 1 1 1 1 1 Watch Dog Timer Counter Register WDTCNT R 0 0 0 0 0 0 0 0 8FH BUZZER Data Register BUZDR R W 1 1 1 1 1 1 1 1 90H P2 Data Register P2 R...

Page 55: ...P1PU R W 0 0 0 0 0 0 0 0 AEH P2 Pull up Resistor Selection Register P2PU R W 0 0 0 0 0 0 0 0 AFH P3 Pull up Resistor Selection Register P3PU R W 0 0 0 0 0 0 0 0 B0H P5 Data Register P5 R W 0 0 0 0 0 0...

Page 56: ...ord Register PSW R W 0 0 0 0 0 0 0 0 D1H P5 Direction Register P5IO R W 0 0 0 0 0 0 D2H P0 Function Selection Low Register P0FSRL R W 0 0 0 0 0 0 0 D3H P0 Function Selection High Register P0FSRH R W 0...

Page 57: ...SI1SAR R W 0 0 0 0 0 0 0 0 EEH P3 Function Selection Register P3FSR R W 0 0 0 0 0 0 0 0 EFH P4 Function Selection Register P4FSR R W 0 0 0 0 0 0 0 F0H B Register B R W 0 0 0 0 0 0 0 0 F1H USI1 Status...

Page 58: ...r 4 PWM Period Low Register T4PPRL R W 1 1 1 1 1 1 1 1 1009H Timer 4 PWM Period High Register T4PPRH R W 0 0 100AH Timer 4 PWM A Duty Low Register T4ADRL R W 0 1 1 1 1 1 1 1 100BH Timer 4 PWM A Duty H...

Page 59: ...W R W R W R W R W R W Initial value 00H B B Register SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Register Low 82H 7 6 5...

Page 60: ...00H CY Carry Flag AC Auxiliary Carry Flag F0 General Purpose User Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set...

Page 61: ...to input mode Set bits of this register will make the pin to output mode Almost bits are cleared by a system reset but some bits are set by a system reset 9 2 3 Pull up Resistor Selection Register PxP...

Page 62: ...lection Register P15DB DFH R W 00H P1 P5Debounce Enable Register P1FSRH D5H R W 00H P1 Function Selection High Register P1FSRL D4H R W 00H P1 Function Selection Low Register P2 90H R W 00H P2 Data Reg...

Page 63: ...I O Data NOTE 1 Do not use the direct bit test and branch instruction for input port More detail information is at chapter 17 2 Instructions on how to use the input port Example Avoid direct input po...

Page 64: ...4 1 0 fx 4096 1 1 Reserved P07DB Configure De bounce of P07 Port 0 Disable 1 Enable P06DB Configure De bounce of P06 Port 0 Disable 1 Enable P05DB Configure De bounce of P05 Port 0 Disable 1 Enable P...

Page 65: ...Description 0 0 I O Port EINT5 function possible when input 0 1 SEG22 Function 1 0 AN5 Function 1 1 PWM4CB Function P0FSRH 3 2 P06 Function Select P0FSRH3 P0FSRH2 Description 0 0 I O Port EINT4 funct...

Page 66: ...rt EINT2 function possible when input 0 1 SEG25 Function 1 0 AN2 Function 1 1 PWM4BA Function P0FSRL 4 3 P03 Function Select P0FSRL4 P0FSRL3 Description 0 0 I O Port EINT1 function possible when input...

Page 67: ...NOTE 1 Do not use the direct bit test and branch instruction for input port More detail information is at chapter 17 2 Instructions on how to use the input port Example Avoid direct input port bit te...

Page 68: ...52 Port 0 Disable 1 Enable P17DB Configure De bounce of P17 Port 0 Disable 1 Enable P16DB Configure De bounce of P16 Port 0 Disable 1 Enable P12DB Configure De bounce of P12 Port 0 Disable 1 Enable P1...

Page 69: ...SS2 function possible when input 0 1 SEG21 Function 1 0 AN6 Function 1 1 Not used P1FSRH 5 4 P16 Function Select P1FSRH5 P1FSRH4 Description 0 0 I O Port EINT7 function possible when input 0 1 SEG20...

Page 70: ...1 SEG17 Function 1 0 AN10 Function 1 1 BUZO Function P1FSRL 5 4 P12Function Select P1FSRL5 P1FSRL4 Description 0 0 I O Port EINT11 function possible when input 0 1 SEG16 Function 1 0 AN11 Function 1...

Page 71: ...7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 R W R W R W R W R W R W R W R W Initial value 00H P2 7 0 I O Data NOTE 1 Do not use the direct bit test and branch instruction for input port More deta...

Page 72: ...R W R W R W R W R W R W R W R W Initial value 00H P2PU 7 0 Configure Pull up Resistor of P2 Port 0 Disable 1 Enable P2OD P2 Open drain Selection Register 93H 7 6 5 4 3 2 1 0 P27OD P26OD P25OD P24OD P2...

Page 73: ...SEG9 Function P2FSRL Port 2 Function Selection Low Register D6H 7 6 5 4 3 2 1 0 P2FSRL5 P2FSRL4 P2FSRL3 P2FSRL2 P2FSRL1 P2FSRL0 R W R W R W R W R W R W Initial value 00H P2FSRL5 P23 Function Select 0...

Page 74: ...a NOTE 1 Do not use the direct bit test and branch instruction for input port More detail information is at chapter 17 2 Instructions on how to use the input port Example Avoid direct input port bit t...

Page 75: ...Port 1 COM3 SEG1 Function P3FSR3 P33 Function select 0 I O Port 1 COM4 SEG2 or COM0 Function P3FSR2 P32 Function Select 0 I O Port 1 COM5 SEG3 or COM1 Function P3FSR1 P31 Function select 0 I O Port 1...

Page 76: ...alue 00H P4 3 0 I O Data NOTE 1 Do not use the direct bit test and branch instruction for input port More detail information is at chapter 17 2 Instructions on how to use the input port Example Avoid...

Page 77: ...SR2 P4FSR1 P4FSR0 R W R W R W R W R W R W R W Initial value 00H P4FSR6 P43 Function Select 0 I O Port SS0 function possible when input 1 VLC0 Function P4FSR 5 4 P42 Function Select P4FSR5 P4FSR4 Descr...

Page 78: ...se the direct bit test and branch instruction for input port More detail information is at chapter 17 2 Instructions on how to use the input port Example Avoid direct input port bit test and branch co...

Page 79: ...t 0 I O Port EINT10 function possible when input 1 SXOUT Function P5FSR 4 3 P53 Function Select P5FSR4 P5FSR3 Description 0 0 I O Port 0 1 SXIN Function 1 0 T0O PWM0O Function 1 1 Not used P5FSR2 P51...

Page 80: ...e registers IE IE1 IE2 and IE3 Each bit of IE IE1 IE2 IE3 register individually enables disables the corresponding interrupt source Overall control is provided by bit 7 of IE EA When EA is set to 0 al...

Page 81: ...nterrupt 18 Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20 Interrupt 3 Interrupt 9 Interrupt 15 Interrupt 21 Interrupt 4 Interrupt 10 Interrupt 16...

Page 82: ...pt source has enable disable bits The External interrupt flag 0 register EIFLAG0 and external interrupt flag 1 register 1 EIFLAG1 provides the status of external interrupts EINT1 Pin EINT3 Pin EINT5 P...

Page 83: ...AG0 6 EIFLAG0 7 Timer 0 overflow Timer 0 Timer 1 Timer 2 Timer 3 IP1 IP IE FLAG10 FLAG11 IE2 T0OVIFR T0IFR T1IFR T2IFR T3IFR FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 EIPOL1 USI0 I2C USI0 Rx USI...

Page 84: ...INT9 IE1 3 10 Maskable 004BH USI0 Tx Interrupt INT10 IE1 4 11 Maskable 0053H External Interrupt 12 INT11 IE1 5 12 Maskable 005BH T0 Overflow Interrupt INT12 IE2 0 13 Maskable 0063H T0 Match Interrupt...

Page 85: ...instruction it needs 3 9 machine cycles to go to the interrupt service routine The interrupt service task is terminated by the interrupt return instruction RETI Once an interrupt request is generated...

Page 86: ...g of Interrupt Enable Register Case b Interrupt flag Register Figure 10 5 Effective Timing of Interrupt Flag Register Interrupt Flag Register Command Next Instruction Next Instruction After executing...

Page 87: ...y than INT1 is occurred Then INT0 is served immediately and then the remain part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be served after...

Page 88: ...Saving Restore Process Diagram and Sample Source Main Task Saving Register Restoring Register Interrupt Service Task INTxx PUSH PSW PUSH DPL PUSH DPH PUSH B PUSH ACC Interrupt_Processing POP ACC POP B...

Page 89: ...12 1 Interrupt Enable Register IE IE1 IE2 IE3 Interrupt enable register consists of global interrupt control bit EA and peripheral interrupt control bits Total 24 peripherals are able to control inter...

Page 90: ...0H Interrupt Enable Register 2 IE3 ABH R W 00H Interrupt Enable Register 3 IP B8H R W 00H Interrupt PriorityRegister IP1 F8H R W 00H Interrupt PriorityRegister 1 EIFLAG0 C0H R W 00H External Interrupt...

Page 91: ...s 0 All Interrupt disable 1 All Interrupt enable INT5E Enable or Disable External Interrupt 0 7 EINT0 EINT7 0 Disable 1 Enable INT4E Enable or Disable USI1 Tx Interrupt 0 Disable 1 Enable INT3E Enable...

Page 92: ...Initial value 00H INT11E Enable or Disable External Interrupt 12 EINT12 0 Disable 1 Enable INT10E Enable or Disable USI0Tx Interrupt 0 Disable 1 Enable INT9E Enable or Disable USI0 Rx Interrupt 0 Disa...

Page 93: ...Timer 1 Match Interrupt 0 Disable 1 Enable INT13E Enable or Disable Timer 0 Match Interrupt 0 Disable 1 Enable INT12E Enable or Disable Timer 0 Overflow Interrupt 0 Disable 1 Enable IE3 Interrupt Ena...

Page 94: ...IP1 IP0 R W R W R W R W R W R W Initial value 00H IP1 Interrupt Priority Register 1 F8H 7 6 5 4 3 2 1 0 IP15 IP14 IP13 IP12 IP11 IP10 R W R W R W R W R W R W Initial value 00H IP 5 0 IP1 5 0 Select In...

Page 95: ...nd branch condition as below if FLAG0 if EIFLAG0 0x01 EIPOL0H External Interrupt Polarity 0High Register A5H 7 6 5 4 3 2 1 0 POL7 POL6 POL5 POL4 R W R W R W R W R W R W R W R W Initial value 00H EIPOL...

Page 96: ...interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or automatically clear by INT_ACK signal Writing 1 has no effect 0 T3 Interrupt no generation 1 T3 Interrupt generation EIFLAG1...

Page 97: ...tively The main sub clock can be also obtained from the external oscillator In this case it is necessary to put the external clock signal into the XIN SXIN pin and open the XOUT SXOUT pin The default...

Page 98: ...N XOUT Main OSC fXIN STOP Mode XCLKE Internal RC OSC 16MHz STOP Mode IRCE fIRC 1 1 1 2 1 4 1 8 M U X WDTRC OSC 5kHz WDTCK Stabilization Time Generation M U X BIT clock WDT clock SXIN SXOUT Sub OSC fSU...

Page 99: ...neratorregister uses clock control for system operation The clock generation consists of System and clock control register and oscillator control register 11 1 5 Register Description for Clock Generat...

Page 100: ...0 1 INT RC 16 1MHz 0 1 0 INT RC 8 2MHz 0 1 1 INT RC 4 4MHz 1 0 0 INT RC 2 8MHz 1 0 1 INT RC 1 16MHz Other values Not used IRCE Control the Operation of the Internal RC Oscillator 0 Enable operation o...

Page 101: ...features During Power On BIT gives a stable clock generation time On exiting Stop mode BIT gives a stable clock generation time As timer function timer interrupt occurrence 11 2 2 Block Diagram BIT Cl...

Page 102: ...5 4 3 2 1 0 BITIFR BITCK1 BITCK0 BCLR BCK2 BCK1 BCK0 R W R W R W R W R W R W R W Initial value 01H BITIFR When BIT Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto cle...

Page 103: ...s up After 1 machine cycle this bit is cleared to 0 automatically The watchdog timer consists of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary counter is equ...

Page 104: ...p Name Address Direction Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R W 00H Watch Dog Timer Control Register Table 11...

Page 105: ...alue 1 NOTE 1 Do not write 0 in the WDTDR register WDTCR Watch Dog Timer Control Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTCK WDTIFR R W R W R W R W R W Initial value 00H WDTEN Control WDT O...

Page 106: ...ts may be composed of 21 bit counter which contains low 14 bit with binary counter and high 7 bit counter in order to raise resolution In WTDR it can control WT clear and set interval value at write t...

Page 107: ...TCR can control the clock source WTCK 1 0 interrupt interval WTIN 1 0 and function enable disable WTEN Also there is WT interrupt flag bit WTIFR 11 4 5 Register Description for Watch Timer WTCNT Watch...

Page 108: ...by INT_ACK signal Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Description 0 0 fWCK 2 7 0 1 fWCK 2 13 1 0 fWCK 2 14...

Page 109: ...r an external clock source EC0 The clock source is selected by clock selection logic which is controlled by the clock selection bits T0CK 2 0 TIMER0 clock source fX 2 4 8 32 128 512 2048 and EC0 In th...

Page 110: ...rnal clock EC0 counts up the timer at the rising edge If the EC0 is selected as a clock source by T0CK 2 0 EC0 port should be set to the input port by P52IO bit P r e s c a l e r fx M U X fx 2 T0CNT 8...

Page 111: ...r 0 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H The timer 0 overflow interrupt is generated...

Page 112: ...00H 01H 02H 4AH FFH FEH 00H T0 Match Interrupt T0 Overflow Interrupt T0DR 1 T0DR 4AH Timer 0 clock Set T0EN T0PWM T0 Match Interrupt 2 T0DR 00H T0PWM T0 Match Interrupt 3 T0DR FFH PWM Mode T0MS 01b F...

Page 113: ...T0O waveform is not available According to EIPOL1 registers setting the external interrupt EINT10 function is chosen Of course the EINT10 pin must be set to an input port T0CDR and T0DR are in the sa...

Page 114: ...flow in Capture Mode T0CNT Interrupt Request FLAG10 XXH Interrupt Interval Period FFH 01H FFH 01H YYH 01H Ext EINT10 PIN Interrupt Request T0IFR FFH FFH YYH 00H 00H 00H 00H 00H T0CNT Value Interrupt R...

Page 115: ...0MS 1 0 2 T0MS 1 0 2 Match signal T0CC Figure 11 13 8 bit Timer 0 Block Diagram 11 5 6 Register Map Name Address Direction Default Description T0CNT B3H R 00H Timer 0 Counter Register T0DR B4H R W FFH...

Page 116: ...R R R Initial value 00H T0CNT 7 0 T0 Counter T0DR Timer 0 Data Register B4H 7 6 5 4 3 2 1 0 T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 R W R W R W R W R W R W R W R W Initial value FFH T0DR 7 0 T...

Page 117: ...er mode 0 1 PWM mode 1 x Capture mode T0CK 2 0 Select Timer 0 clock source fx is a system clock frequency T0CK2 T0CK1 T0CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1 0 0 fx 128 1 0 1...

Page 118: ...er 1 outputsPWM wave form through PWM1Oport in the PPG mode T1EN P1FSRL 5 4 T1MS 1 0 T1CK 2 0 Timer 1 1 11 00 XXX 16 bit Timer Counter Mode 1 00 01 XXX 16 bit Capture Mode 1 11 10 XXX 16 bit PPG Mode...

Page 119: ...interrupt block A Match Buffer Register A A Match T1CC Reload Pulse Generator T1O R T1EN 3 T1CK 2 0 2 T1MS1 T1MS0 T1CC 0 0 X T1CK2 T1CRL X ADDRESS BAH INITIAL VALUE 0000_0000B T1CK1 T1CK0 T1IFR T1POL...

Page 120: ...T1BDRL According toEIPOL1 registers setting the external interrupt EINT11 function is chosen Of course the EINT11 pin must be set as an input port A Match T1CC T1EN P r e s c a l e r fx M U X fx 2 fx...

Page 121: ...apture Mode T1CNTH L Interrupt Request FLAG11 XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT11 PIN Interrupt Request T1IFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H T1CNTH L Value Interr...

Page 122: ...fx 512 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear B Match Edge Detector T1ECE EC1 Buffer Register B Comparator 16 bit A Data Register T1ADRH...

Page 123: ...T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 1 clock Counter T1ADRH L T1 Interrupt PWM1O B Match One shot Mode T1MS 10b and...

Page 124: ...PWM1O R EINT11 T1CNTR T1EN 3 T1CK 2 0 Clear EIPOL1 5 4 FLAG11 EIFLAG1 2 INT_ACK Clear To interrupt block 2 2 T1MS 1 0 2 Edge Detector T1ECE EC1 To Timer 2 block A Match T1CC T1EN A Match T1CC T1EN Fig...

Page 125: ...R W R W Initial value FFH T1ADRH 7 0 T1 A Data High Byte T1ADRL Timer 1 A Data Low Register BCH 7 6 5 4 3 2 1 0 T1ADRL7 T1ADRL6 T1ADRL5 T1ADRL4 T1ADRL3 T1ADRL2 T1ADRL1 T1ADRL0 R W R W R W R W R W R W...

Page 126: ...ble 1 Timer 1 enable Counter clear and start T1MS 1 0 Control Timer 1 Operation Mode T1MS1 T1MS0 Description 0 0 Timer counter mode T1O toggle at A match 0 1 Capture mode The A match interrupt can occ...

Page 127: ...k EC1 T1IFR When T1 Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 T1 Interrupt no generation 1 T1 Interrupt generat...

Page 128: ...nd T1 A Match timer 1 A match signal The clock source is selected by clock selection logic which is controlled by the clock selection bits T2CK 2 0 TIMER 2 clock source fX 1 fX 2 fX 4 fX 8 fX 32 fX 12...

Page 129: ...ccurs The T2CNTH T2CNTL valuesare automatically cleared by match signal It can be also cleared by software T2CC T2MS 1 0 T2POL A Match T2CC T2EN P r e s c a l e r fx M U X fx 2 fx 4 fx 32 fx 128 fx 51...

Page 130: ...Figure 11 23 16 bit Timer Counter 2 Example T2CNTH L Value Timer 2 T2IFR Interrupt TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Period PCP x n 1 0 Count Pulse Period PCP Up count Match with T2ADRH L Occur In...

Page 131: ...ailable According to EIPOL1 registers setting the external interrupt EINT12 function is chosen Of course the EINT12 pin must be set to an input port A Match T2CC T2EN P r e s c a l e r fx M U X fx 2 f...

Page 132: ...apture Mode T2CNTH L Interrupt Request FLAG12 XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT12 PIN Interrupt Request T2IFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H T2CNTH L Value Interr...

Page 133: ...Comparator 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear B Match T1 A Match Buffer Register B Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_ACK Clear To interrup...

Page 134: ...T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 2 clock Counter T2ADRH L T2 Interrupt PWM2O B Match One shot Mode T2MS 10b and...

Page 135: ...EN 3 T2CK 2 0 Clear EIPOL1 7 6 FLAG12 EIFLAG1 3 INT_ACK Clear To interrupt block 2 2 T2MS 1 0 2 T1 A Match A Match T2CC T2EN A Match T2CC T2EN NOTE 1 T1 A Match is a pulse for the timer 2 clock source...

Page 136: ...R W R W R W Initial value FFH T2ADRH 7 0 T2 A Data High Byte T2ADRL Timer 2 A Data Low Register C4H 7 6 5 4 3 2 1 0 T2ADRL7 T2ADRL6 T2ADRL5 T2ADRL4 T2ADRL3 T2ADRL2 T2ADRL1 T2ADRL0 R W R W R W R W R W...

Page 137: ...ble 1 Timer 2 enable Counter clear and start T2MS 1 0 Control Timer 2Operation Mode T2MS1 T2MS0 Description 0 0 Timer counter mode T2O toggle at A match 0 1 Capture mode The A match interrupt can occu...

Page 138: ...0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 T1 A Match T2IFR When T2 Match Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 T2i...

Page 139: ...3 0 Also the timer counter 4 can use more clock sources than timer counter 3 TIMER 3 clock source fX 2 fX 4 fX 8 fX 32 fX 128 fX 512 fX 2048 and EC3 TIMER 4 clock source fX 1 fX 2 fX 4 fX 8 fX 16 fX 3...

Page 140: ...g edge If the EC3 is selected as a clock source by T3CK 2 0 EC3 port should be set to the input port by P00IO bit Timer 4 can t use the external EC3 clock T3EN T3CR 1 ADDRESS 1000H ESFR INITIAL VALUE...

Page 141: ...bit must be set to 1 Timer 3 is LSB 8 bit the timer 4 is MSB 8 bit The external clock EC3 counts up the timer at the rising edge f the EC3 is selected as a clock source by T3CK 2 0 EC3 port should be...

Page 142: ...ically cleared by match signal This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer The capture result is loaded into T...

Page 143: ...t Timer 4 Counter T4DR 8Bit Comparator To interrupt block T4O 8 bit Timer 4 Data Register Clear Match T4CAPR 8Bit Clear EINT1 EIPOL0L 3 2 FLAG0 EIFLAG0 1 S W Clear To interrupt block 2 T4ST 8 bit Time...

Page 144: ...t EC3 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T3CK 2 0 T3CN 16 bit Timer 3 Counter T4DR T3DR 16Bit Comparator T3IFR To interrupt block T3O 16 bit Timer 3 Data Register INT_ACK Clear Clear Match T4CAPR...

Page 145: ...4ADRL X Source Clock Resolution Frequency T4CK 3 0 0001 250ns T4CK 3 0 0010 500ns T4CK 3 0 0100 2us 10 bit 3 9kHz 1 95kHz 0 49kHz 9 bit 7 8kHz 3 9kHz 0 98kHz 8 bit 15 6kHz 7 8kHz 1 95kHz 7 bit 31 2kHz...

Page 146: ...Register T4CDRH T4CDRL PWM Output Control C ch PWM4CA PWM Delay Control C ch PWM4CB A Match B Match C Match Interrupt Generator A Match B Match C Match Bottom Underflow To interrupt block FORCA T4PCR...

Page 147: ...l C ch PWM4CA PWM Delay Control C ch PWM4CB A Match Interrupt Generator A Match B Match C Match Bottom Underflow To interrupt block FORCA T4PCR2 1 ADDRESS 1004H ESFR INITIAL VALUE 0000_0000B PAAOE PAB...

Page 148: ...ization circuit So the update data is written before 3 cycle of timer clock to get the right output waveform T4CNT 00 01 02 03 04 P02 PWM4AA POLAA 1 T4CR 03H 2 us T4PPRH 00H T4PPRL 0EH T4ADRH 00H T4AD...

Page 149: ...waveform in Back to Back mode at 4 MHz T4CNT 00 01 02 03 04 P02 PWM4AA POLAA 1 T4CR 03H 2 us T4PPRH 00H T4PPRL 0BH T4ADRH 00H T4ADRL 05H 09 08 07 06 05 0A 0B 0B 0A 06 07 08 09 02 03 04 05 01 00 00 01...

Page 150: ...ion by the software During PHLT bit being 1 PWM output becomes a reset value and internal counter becomes reset as 0 Without changing PWM setting temporarily it is able to stop PWM In case of T4CNT wh...

Page 151: ...at the inversion outputs of A B C channel have the same A ch output waveform According to POLAA BB CC it is able to control the inversion of outputs Figure 11 42 Example of Force Drive All Channel wit...

Page 152: ...BA BB output of the B channel duty register a CA CB output of the C channel duty register are controlled respectively If the UALL bit is set to 1 it is updated B C channel duty at the same time when...

Page 153: ...dge so the duty is reduced as the time delay In POLAA BA CA setting to 0 the delay is applied to the falling edge In POLAA BA CA setting to 1 the delay is applied to the rising edge It can produce a p...

Page 154: ...SS 1010H ESFR INITIAL VALUE 0000_0000B FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T4PCR2 0 X X X X X X HZCLR POLBO POLAA POLAB POLBA POLBB POLCA T4PCR3 X X 1 1 X X X X T4DLYAA3 T4DLYAA2 T4DLYAA1 T4DLYA...

Page 155: ...AG0 EIFLAG0 0 INT_ACK Clear To interrupt block 2 T3MS T3ST 8 bit Timer 3 Capture Register T4CNT 8Bit 4 T4CK 3 0 8 bit Timer 4 Counter T4DR 8Bit Comparator To interrupt block T4O 8 bit Timer 4 Data Reg...

Page 156: ...x M U X fx 2 fx 4 fx 16 fx 32 fx 64 fx 8 fx 1 Comparator 10 bit Counter 2Bit T4CNT 10 bit A Data Register T4ADRH T4ADRL Control Up Down Comparator T4PPRH T4PPRL 10Bit Period Match PWM Output Control A...

Page 157: ...PWM B Duty Low Register T4CDRH 100FH ESFR R W 00H Timer 4 PWM C Duty High Register T4CDRL 100EH ESFR R W 7FH Timer 4 PWM C Duty Low Register T4DLYA 1010H ESFR R W 00H Timer 4 PWM A Delay Register T4D...

Page 158: ...se Timer mode only 1001H ESFR 7 6 5 4 3 2 1 0 T3CNT7 T3CNT6 T3CNT5 T3CNT4 T3CNT3 T3CNT2 T3CNT1 T3CNT0 R R R R R R R R Initial value 00H T3CNT 7 0 T3 Counter T3DR Timer 3 Data Register Write Case 1001H...

Page 159: ...match 1 Capture mode the match interrupt can occur T3CK 2 0 Select Timer 3 clock source fx is main system clock frequency T3CK2 T3CK1 T3CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1...

Page 160: ...imer 4 interrupt mask register T4MSK 11 8 12 Register Description for Timer Counter 4 T4PPRH Timer 4 PWM Period High Register 6 ch PWM mode only 1009H ESFR 7 6 5 4 3 2 1 0 T4PPRH1 T4PPRH0 R W R W Init...

Page 161: ...mer 4 PWM C Duty Low Register 6 ch PWM mode only 100EH ESFR 7 6 5 4 3 2 1 0 T4CDRL7 T4CDRL6 T4CDRL5 T4CDRL4 T4CDRL3 T4CDRL2 T4CDRL1 T4CDRL0 R W R W R W R W R W R W R W R W Initial value 7FH T4CDRL 7 0...

Page 162: ...nd Capture mode only 1013H ESFR 7 6 5 4 3 2 1 0 T4DR7 T4DR6 T4DR5 T4DR4 T4DR3 T4DR2 T4DR1 T4DR0 R W R W R W R W R W R W R W R W Initial value FFH T4DR 7 0 T4 Data T4CAPR Timer 4Capture Data Register R...

Page 163: ...pture mode the match interrupt can occur T4CN Control Timer 4 Count Pause Continue 0 Temporary count stop 1 Continue count T4ST Control Timer 4 Start Stop 0 Counter stop 1 Clear counter and start T4CK...

Page 164: ...K input pin Where x A B and C BMOD Control Back to Back Mode Operation 0 Disable back to back mode up count only 1 Enable back to back mode up down count only PHLT Control Timer 4 PWM Operation 0 Run...

Page 165: ...xB pins are output according to the only T4ADR registers Where x A B and C PAAOE Select Channel PWM4AA Operation 0 Disable PWM4AA output 1 Enable PWM4AA output PABOE Select Channel PWM4AB Operation 0...

Page 166: ...g when disable POLAB POLBB POLCB bits where x A B and C POLAA Configure PWM4AA Channel Polarity 0 Start at high level This pin is low level when disable 1 Start at low level This pin is high level whe...

Page 167: ...no occurrence 1 PWM B ch match occurrence ICMC Timer 4 PWM C ch Match Interrupt Status Write 0 to this bit for clear 0 PWM C ch match no occurrence 1 PWM C ch match occurrence T4MSK Timer 4 Interrupt...

Page 168: ...k divided by prescaler BUZDR 7 0 Buzzer Frequency kHz BUZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 125kHz 62 5kHz 31 25kHz 15 625kHz 0000_0001 62 5kHz 31 25kHz 15 625kHz 7 812kHz 1111...

Page 169: ...Buzzer Driver BUZDR Buzzer Data Register 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bits control the...

Page 170: ...t master slave mode can select serial clock SCK2 polarity phase and whether LSB first data transfer or MSB first data transfer 11 10 2 Block Diagram P r e s c a l e r fx M U X fx 4 fx 8 fx 32 fx 64 fx...

Page 171: ...4 SS2 pin function 1 When the SPI 2 is configured as a Slave the SS2 pin is always input If LOW signal come into SS2 pin the SPI 2 logic is active And if HIGH signal come into SS2 pin the SPI 2 logic...

Page 172: ...ut D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SCK2 CPOL 0 SS2 SPIIFR Figure 11 50 SPI 2 Transmit Receive Timing Diagram at CPHA 0 SCK2 CPOL 1 MISO2 MOSI2 Output MOSI2 MISO2 Input D0 D1 D2 D3 D4 D...

Page 173: ...Map 11 10 7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register SPICR SPI 2 status register SPISR and SPI 2 data register SPIDR 11 10 8 Register Description for SPI 2 SPID...

Page 174: ...ct 0 SPI 2 Interrupt no generation 1 SPI 2 Interrupt generation WCOL This bit is set if any data are written to the data register SPIDR during transfer This bit is cleared when the status register SPI...

Page 175: ...s two bits control the serial clock SCK2 mode Clock polarity CPOL bit determine SCK2 s value at idle mode Clock phase CPHA bit determine if data are sampled on the leading or trailing edge of SCK2 CPO...

Page 176: ...t to xxx The register ADCDRH and ADCDRL contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCDRH and ADCDRL the A D conversion status bit AFLAG...

Page 177: ...S AN1 AN2 AN14 AN15 ADCIFR AFLAG INT_ACK Clear Clear To interrupt block MUX VDD Start M U X T4 A match event signal T4 B match event signal T4 C match event signal REFSEL TRIG 2 0 3 ADST T1 A match si...

Page 178: ...ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCO11 ADCO10 ADCO9 A...

Page 179: ...ster Table 11 18 ADC Register Map 11 11 6 ADC Register Description The ADC register consists of A D converter data highregister ADCDRH A D converter datalowregister ADCDRL A D converter control high r...

Page 180: ...verter Control High Register 9DH 7 6 5 4 3 2 1 0 ADCIFR TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 R W R W R W R W R W R W R W Initial value 00H ADCIFR When ADC interrupt occurs this bit becomes 1 For clea...

Page 181: ...ADC Conversion Start and auto clear REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 External Reference AVREF AFLAG A D Converter Operation State This bit is cleared to 0 when the S...

Page 182: ...s register 1 2 USI baud rate generation register USI data register USI SDA hold time register USI SCL high period register USI SCL low period register and USI slave address register USInCR1 USInCR2 US...

Page 183: ...generator transmitter and receiver The clock generation logic consists of synchronization logic for external clock input used by synchronizing or SPI slave operation and the baud rate generator for as...

Page 184: ...Shift Register TXSR USInDR USInTX8 Tx USInP 1 0 M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn RXCIEn WAKEIEn WAKEn At Stop mode To interrupt block SCLK fx Sys...

Page 185: ...mode is controlled by the DBLSn bit in the USInCR2 register The MASTERn bit in USInCR3 register controls whether the clock source is internal master mode output pin or external slave mode input pin T...

Page 186: ...When synchronous or SPI mode is used the SCKn pin will be used as either clock input slave or clock output master Data sampling and transmitter is issued on the different edge of SCKn clock each other...

Page 187: ...top bit A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an idle...

Page 188: ...ill transfer one complete frame according to the settings of control registers If the 9 bit characters are used in asynchronous or synchronous operation mode the ninth bit must be written to the USInT...

Page 189: ...input pin in slave mode or can be configured as SSn output pin in master mode This can be done by setting USInSSEN bit in USInCR3 register 11 12 10 1 USIn UART Receiving RX data When UART is in synchr...

Page 190: ...The FEn flag is 0 when the stop bit was correctly detected as 1 and the FEn flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync conditions betwe...

Page 191: ...g bits and removing the noise of RXDn pin The next figure illustrates the sampling process of the start bit of an incoming frame The sampling rate is 16 times of the baud rate in normal mode and 8 tim...

Page 192: ...ceived bit is considered to a logic 0 and if more than 2 samples have high levels the received bit is considered to a logic 1 The data recovery process is then repeated until a complete frame is recei...

Page 193: ...OSIn for compatibility to other SPI devices 11 12 12 USIn SPI Clock Formats and Timing To accommodate a wide variety if synchronous serial peripherals from different manufacturers the USIn has a clock...

Page 194: ...inputs respectively At the second SCKn edge the USIn shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave respectively Unlike the case of CPHAn 1 when CPHAn 0 th...

Page 195: ...the MOSIn and MISOn output of the master and slave respectively When CPHAn 1 the slave s SSn input is not required to go to its inactive high level between transfers Because the SPI logic reuses the U...

Page 196: ...R Tx I N T E R N A L B U S L I N E M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn Baud Rate Generator USInBD TXEn SCLK fx System clock MISOn MOSIn M U X MASTERn...

Page 197: ...2C bus standard Multi master operation Up to 400kHz data transfer read speed 7 bit address Both master and slave operation Bus busy detection 11 12 15 USIn I2C Bit Transfer The data on the SDAn line m...

Page 198: ...and repeated START conditions are functionally identical Figure 11 68 START and STOP Condition USIn 11 12 17 USIn I2C Data Transfer Every byte put on the SDAn line must be 8 bits long The number of b...

Page 199: ...Bus USIn 11 12 19 USIn I2C Synchronization Arbitration Clock synchronization is performed using the wired AND connection of I2C interfaces to the SCLn line This means that a HIGH to LOW transition on...

Page 200: ...terrupt source bits in the USInST2 register are cleared to 0b When I2C interrupt occurs the SCLn line is hold LOW until clearing 0b all interrupt source bits in USInST2 register When the IICnIFR flag...

Page 201: ...ce When I2C loses bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits in idle state or can be operate as an addressed slave To operate as a slave when the MLOSTn b...

Page 202: ...R 2 Master stops data transfer even if it receives ACK signal from slave In this case set the STOPCn bit in USInCR4 3 Master transmits repeated START condition with not checking ACK signal In this cas...

Page 203: ...e When I2C loses bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits in idle state or can be operate as an addressed slave To operate as a slave when the MLOSTn bi...

Page 204: ...e no ACK signal is detected master terminates data transfer In this case set the STOPCn bit in USInCR4 4 No ACK signal is detected and master transmits repeated START condition In this case load SLAn...

Page 205: ...er START condition Else if the address equals to USInSLA 6 0 bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to USIn...

Page 206: ...ART condition Else if the address equals to SLAn bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to SLAn bits when t...

Page 207: ...Slave Address Register USInSAR General Call And Address Detector USInGCE STOP START Condition Generator STOPCn STARTCn ACK Signal Generator ACKnEN RXACKn GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn...

Page 208: ...ation Register USI1DR F5H R W 00H USI1 Data Register USI1SDHR F4H R W 01H USI1 SDA Hold Time Register USI1SCHR F7H R W 3FH USI1 SCL High Period Register USI1SCLR F6H R W 3FH USI1 SCL Low Period Regist...

Page 209: ...mode NOTE 1 In common with USInSAR register USInBD register is used for slave address register when the USIn I2C mode USInDR USIn Data Register For UART SPI and I2C mode E5H F5H n 0 1 7 6 5 4 3 2 1 0...

Page 210: ...The SDAn is changed after tSCLK X USInSDHR 2 in master mode So to insure operation in slave mode the value 4 tSCLK X USInSDHR 2 must be smaller than the period of SCL USInSCHR USInSCL High Period Regi...

Page 211: ...SCLK the system clock and the period is calculated by the formula tSCLK X 4 X USInSCLR 2 where tSCLK is the period of SCLK USInSAR USIn Slave Address Register For I2C mode DDH EDH n 0 1 7 6 5 4 3 2 1...

Page 212: ...of data bits in frame USInS2 USInS1 USInS0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORDn This bit in the same bit position...

Page 213: ...RXCn is inhibited use polling 1 When RXCn is set request an interrupt WAKEIEn Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXDn goes to low level an interrupt...

Page 214: ...UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USInSSEN This bit controls the SSn pin operation only SPI mode 0 Disable 1 Enable The SSn pin should be a...

Page 215: ...terrupt Enable bit for I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACKnEN Controls ACK signal Generation at ninth SCLn period 0 No ACK signal is generated SDAn 1...

Page 216: ...ate a RXCn interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag is set when the RXDn pin is detected low while the CPU is in STO...

Page 217: ...P condition is detected 1 STOP condition is detected SSELn NOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as a slave 1 I2C is addressed by other master and acts as a...

Page 218: ...lator Frequencies Baud Rate bps fx 1 00MHz fx 1 8432MHz fx 2 00MHz USI0BD USI1BD ERROR USI0BD USI1BD ERROR USI0BD USI1BD ERROR 2400 25 0 2 47 0 0 51 0 2 4800 12 0 2 23 0 0 25 0 2 9600 6 7 0 11 0 0 12...

Page 219: ...LCD Control Register LCDCRH L The LCLK 1 0 determines the frequency of COM signal scanning of each segment output A RESET clears the LCD control register LCDCRH and LCDCRL values to logic 0 The LCD d...

Page 220: ...ta and drive method Therefore display patterns can be changed by only overwriting the contents of the display external data area with a program Figure 11 99 shows the correspondence between the displa...

Page 221: ...Frame VDD VSS 0 1 COM1 SEG1 COM0 SEG0 COM0 VSS VLC0 VLC2 VLC1 VLC3 COM0 COM1 SEG0 SEG1 SEG3 0 1 SEG2 SEG0 VSS VSS VLC0 VLC2 VLC1 VLC3 VLC2 VLC1 VLC3 VLC0 VSS VSS VLC0 VLC2 VLC1 VLC3 VLC0 VLC2 VLC1 VLC...

Page 222: ...rame VDD VSS 0 1 COM1 SEG2 COM0 SEG1 COM0 VLC2 VLC3 VLC0 VLC1 SEG1 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 0 1 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3...

Page 223: ...me VDD VSS 0 1 COM1 SEG3 COM0 SEG2 COM0 VLC2 VLC3 VLC0 VLC1 SEG2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC...

Page 224: ...9 S E G 1 0 1 Frame VDD VSS 0 COM1 SEG7 COM0 SEG6 COM0 VLC2 VLC0 VLC1 SEG6 VSS COM2 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC...

Page 225: ...1 VLC2 VLC3 LCTEN DISP VSS R VLC0 VLC1 VLC2 VLC3 VLCD 1 3 BIAS VLC0 VLC1 VLC2 VLC3 R Contrast Controller LCTEN DISP Contrast Controller LCTEN DISP Contrast Controller LCTEN DISP Contrast Controller R...

Page 226: ...tors should be connected like the above figure and the needed bias pins should be selected as the LCD bias function pins VLC0 VLC1 VLC2 and VLC3 by P4FSR register 5 When it is 1 2 bias the P43 VLC0 an...

Page 227: ...ram 11 13 6 Register Map Name Address Direction Default Description LCDCRH 9AH R W 00H LCD Driver Control High Register LCDCRL 99H R W 00H LCD Driver Control Low Register LCDCCR 9BH R W 00H LCD Driver...

Page 228: ...s are outputted through the P33 P30 NOTE 1 The COM0 COM1 COM2 COM3 signals can be outputted through the P33 P32 P31 P30 respectively 2 For example the COM0 signal may be outputted to P33 pin if the P3...

Page 229: ...ias RLCD 1 0 0 0 1 2Duty 1 2Bias 2xRLCD Other values Not available LCLK 1 0 LCD Clock Select When fWCK Watch timer clock 32 768kHz LCLK1 LCLK0 Description 0 0 fLCD 128Hz 0 1 fLCD 256Hz 1 0 fLCD 512Hz...

Page 230: ...x 16 28 step 0 1 0 0 VLC0 VDD x 16 27 step 0 1 0 1 VLC0 VDD x 16 26 step 0 1 1 0 VLC0 VDD x 16 25 step 0 1 1 1 VLC0 VDD x 16 24 step 1 0 0 0 VLC0 VDD x 16 23 step 1 0 0 1 VLC0 VDD x 16 22 step 1 0 1...

Page 231: ...ock Timer0 4 Operates Continuously Halted Only when the Event Counter Mode is Enabled Timer operates Normally ADC Operates Continuously Stop BUZ Operates Continuously Stop SPI Operates Continuously On...

Page 232: ...and peripherals are operated normally but CPU stops It is released by reset or interrupt To be released by interrupt interrupt should be enabled before IDLE mode If using reset because the device bec...

Page 233: ...th the sub clock The source for exit from STOP mode is hardware reset and interrupts The reset re defines all the control registers When exit from STOP mode enough oscillation stabilization time is re...

Page 234: ...he STOP mode isreleased by the interrupt which each interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP mode is released...

Page 235: ...er 87H 7 6 5 4 3 2 1 0 PCON7 PCON3 PCON2 PCON1 PCON0 R W R W R W R W R W Initial value 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal operation NOTE 1 To ente...

Page 236: ...l Registers Table 13 1 Reset State 13 2 Reset Source The MC96F6432S has five types of reset sources The following is the reset sources External RESETB Power ON RESET POR WDT Overflow Reset In the case...

Page 237: ...power the POR Power On Reset has a function to reset the device If POR is used it executes the device RESET function instead of the RESET IC or the RESET circuits Figure 13 3 Fast VDD Rising Time Figu...

Page 238: ...Read POR VDD Input Internal OSC VDD Internal nPOR PAD RESETB BIT for Configure LVR_RESETB BIT for Reset INT OSC 8 MHz 8 INT OSC 8 MHz RESET_SYSB Configure Read 1us X 256 X 28h about 10ms 1us X 4096 X...

Page 239: ...Configure option read Slew Rate 0 05V ms Configure option read point about 1 5V 1 6V Configure Value is determined by Writing Option Rising section to Reset Release Level 16ms point after POR or Ext_r...

Page 240: ...the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 13 7 Timing Diagram after RESET Fig...

Page 241: ...44V 2 59V 2 75V 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the LVREN bit is set to...

Page 242: ...g when BOD RESET VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8MHz 8 INT OSC 8MHz RESET_SYSB Config Read 1us X 256 X 28h about 10ms 1us X 4096 X 4h about 16ms F1 00 01...

Page 243: ...9 Register Map Name Address Direction Default Description RSTFR E8H R W 80H Reset Flag Register LVRCR D8H R W 00H Low Voltage Reset Control Register LVICR 86H R W 00H Low Voltage Indicator Control Re...

Page 244: ...is bit or by Power On Reset 0 No detection 1 Detection LVRF Low Voltage Reset flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection NOTE 1 When the Power O...

Page 245: ...is 0 the LVREN bit is not effect by stop mode to release LVRVS 3 0 LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 0 0 0 0 1 60V 0 0 0 1 2 00V 0 0 1 0 2 10V 0 0 1 1 2 20V 0 1 0 0 2 32V 0 1...

Page 246: ...H LVIF Low Voltage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVILS 3 0 LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0 Description 0 0 0 0 2 00V 0 0 0 1 2...

Page 247: ...quipped with on chip debugger We recommend to develop and debug program with MC96F6432 On chip debug system of MC96F6432 can be used for programming the non volatile memories and on chip debugging Det...

Page 248: ...Including Break Instruction Single Step Break Program Memory Break Points on Single Address Programming of Flash EEPROM Fuses and Lock Bits through the two wire Interface On chip Debugging Supported b...

Page 249: ...e bit as 0 when transmission for 8 bit data and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledg...

Page 250: ...3 Data Transfer on the Twin Bus 14 2 2 2 Bit Transfer Figure 14 4 Bit Transfer on the Serial Bus data line stable data valid except Start and Stop change of data allowed DSDA DSCL St Sp START STOP DS...

Page 251: ...ocedure Start wait start HIGH Host PC DSCL OUT Target Device DSCL OUT DSCL wait HIGH Maximum 5 TSCLK Internal Operation Acknowledge bit transmission minimum 1 TSCLK for next byte transmission Acknowle...

Page 252: ...directional I O Figure 14 8 Connection of Transmission DSCL OUT DSDA OUT DSDA IN DSCL Debugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA IN Host Machine Master Target Device Slave...

Page 253: ...he flash memory can be read by MOVC instruction and it can be programmed in serial ISP mode or user program mode Flash Size 32Kbytes Single power supply program and erase Command interface for fast pr...

Page 254: ...F80H 07F7FH 07F40H Sector 509 07F40H 07F3FH Sector 508 Sector 2 00080H 0007FH 00040H Sector 1 00040H 0003FH 00000H Sector 0 00000H 00080H 8000H 803FH ROM Address Accessed by MOVX instruction only Page...

Page 255: ...lash Identification Register FMCR FEH R W 00H Flash Mode Control Register Table 15 1 Flash Memory Register Map 15 1 4 Register Description for Flash Memory Control and Status Flash control register co...

Page 256: ...l value 00H FSADRM 7 0 Flash Sector Address Middle FSADRL Flash Sector Address Low Register FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R W R W R W R W R W R W...

Page 257: ...upt is on disable state regardless of the IE 7 EA bit FMCR2 FMCR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value Clear all 64bytes to 0 0 1 0 Select...

Page 258: ...as are available only when the PAEN bit is cleared to 0 that is enable protection area at the configure option 2 if it is needed If the protection area isn t enabled PAEN 1 this area can be used as a...

Page 259: ...tion This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Address is 8000H MOV DPL 0 Pgbuf_clr...

Page 260: ...n must be needed NOP Dummy instruction This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Ad...

Page 261: ...nstruction must be needed NOP Dummy instruction This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 5 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A Write data to page buff...

Page 262: ...riteErase MOV A ID_DATA_3 CJNE A UserID3 No_WriteErase MOV FMCR 0x 0x03 if write 0x02 if erase RET No_WriteErase MOV FIDR 00H MOV UserID1 00H MOV UserID2 00H MOV UserID3 00H MOV Flash_flag 00H RET If...

Page 263: ...Work2 CALL ID_write CALL Work3 CALL Flash_erase CALL Flash_write ID_wire MOV A 38H CJNE A Flash_flag1 No_write_ID MOV A 75H CJNE A Flash_flag2 No_write_ID MOV UserID1 ID_DATA_1 Write Uiser ID1 MOV A 3...

Page 264: ...ase for flash memory to be erased by malfunction noise and power off Figure 15 2 Flow of Protection for Invalid Erase Write Start Work1 Set Flags Write UserID1 2 3 Clear the Flag Clear UserID1 2 3 Wri...

Page 265: ...k the UserID for to prevent the invalid work Note 3 Set flash mode control register FMCR NOTE Please refer to the chapter Protection for Invalid Erase Write Program Tip Code Write Protection MOV FIDR...

Page 266: ...on 0 Disable 1 Enable RSTS Select RESETB pin 0 Disable RESETB pin P55 1 Enable RESETB pin CONFIGURE OPTION 2 ROM Address 003EH 7 6 5 4 3 2 1 0 PAEN PASS1 PASS0 Initial value 00H PAEN Enable Specific A...

Page 267: ...t byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F SUBB A d...

Page 268: ...1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A dir Exclusive OR d...

Page 269: ...A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 83 MOVX A Ri Move external data A8 to A 1 2 E2 E3 MOVX A DPTR Move external data A16 to A 1 2 E0 MOVX Ri...

Page 270: ...mpare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 DF DJNZ dir rel Decrement direct byte...

Page 271: ...error by using compare jump instructions If input signal is fixed there is no error in using compare jump instructions Error status example while 1 if P00 1 P10 1 else P10 0 P11 1 zzz JNB 080 0 xxx i...

Page 272: ...opy the input port as internal parameter or carry bit and then use compare jump instruction bit tt while 1 tt P00 if tt 0 P10 1 else P10 0 P11 1 zzz MOV C 080 0 input port use internal parameter MOV 0...

Page 273: ...d by a 100pF capacitor through 1 5k Ohms resistance Machine Model stresses devices by sudden application of a high voltage supplied by a 200pF capacitor through very low 0 Ohm resistance 2 ESD Test Ci...

Page 274: ...conductor Co Ltd 5 ESD Test Method I O Pin to Pin Mode I O pins are zapped pin by pin I O pins which are not zapped are grounded All power pins VDD and VSS are floated 6 ESD Class HBM Human Body Model...

Page 275: ...the flags in program and check the flags in main loop at the end When the Flash Erase Write is executed check the flags If not matched do not execute Check the range of Flash Sector Address If the fla...

Page 276: ...Write Flash Set User_ID1 Working Check User_ID1 Set User_ID2 Working Check User_ID2 Set User_ID3 Working Yes Yes Yes No No No Write Flash Clear User_ID1 2 3 Clear FIDR Clear FMCR Set FSADRH M L to Dum...

Page 277: ...e Write in flash Set to Dummy address after Erase Write Even if invalid work occurred it will be Erase Write in Dummy address in flash Check Flags If every flag User_ID1 2 3 LVI Flash Address Min Max...

Page 278: ...aracteristics 29 7 6 High Internal RC Oscillator Characteristics 29 7 7 Internal Watch Dog Timer RC Oscillator Characteristics 30 7 8 LCD Voltage Characteristics 30 7 9 DC Characteristics 31 7 10 AC C...

Page 279: ...errupt Controller 80 10 1 Overview 80 10 2 External Interrupt 82 10 3 Block Diagram 83 10 4 Interrupt Vector Table 84 10 5 Interrupt Sequence 85 10 6 Effective Timing after Controlling Interrupt Bit 8...

Page 280: ...Counter Mode 118 11 6 3 16 bit Capture Mode 120 11 6 4 16 bit PPG Mode 122 11 6 5 Block Diagram 124 11 6 6 Register Map 124 11 6 7 Timer Counter 1 Register Description 125 11 6 8 Register Description...

Page 281: ...12 9 3 USIn UART Parity Generator 189 11 12 9 4 USIn UART Disabling Transmitter 189 11 12 10 USIn UART Receiver 189 11 12 10 1 USIn UART Receiving RX data 189 11 12 10 2 USIn UART Receiver Flag and In...

Page 282: ...tion for Reset Operation 244 14 On chip Debug System MC96F6432 ONLY 247 14 1 Overview 247 14 1 1 Description 247 14 1 2 Feature 248 14 2 Two Pin External Interface 249 14 2 1 Basic Transmission Packet...

Page 283: ...F6432S ABOV Semiconductor Co Ltd 17 1 Instruction Table 267 17 2 Instructions on how to use the input port 271 17 3 ESD Test Method 273 17 4 Flash Protection for Invalid Erase Write 275 Table of conte...

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