64
MC96F6432S
ABOV Semiconductor Co., Ltd.
P0OD (P0 Open-drain Selection Register): 91H
7
6
5
4
3
2
1
0
P07OD
P06OD
P05OD
P04OD
P03OD
P02OD
P01OD
P00OD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
P0OD[7:0]
Configure Open-drain of P0 Port
0
Push-pull output
1
Open-drain output
P0DB (P0 De-bounce Enable Register): DEH
7
6
5
4
3
2
1
0
DBCLK1
DBCLK0
P07DB
P06DB
P05DB
P04DB
P03DB
P02DB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
DBCLK[1:0]
Configure De-bounce Clock of Port
DBCLK1 DBCLK0 Description
0
0
fx/1
0
1
fx/4
1
0
fx/4096
1
1
Reserved
P07DB
Configure De-bounce of P07 Port
0
Disable
1
Enable
P06DB
Configure De-bounce of P06 Port
0
Disable
1
Enable
P05DB
Configure De-bounce of P05 Port
0
Disable
1
Enable
P04DB
Configure De-bounce of P04 Port
0
Disable
1
Enable
P03DB
Configure De-bounce of P03Port
0
Disable
1
Enable
P02DB
Configure De-bounce of P02 Port
0
Disable
1
Enable
NOTE)
1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the
signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge.
3. The port de-bounce is automatically disabled at stop mode and recovered after stop mode release.
Summary of Contents for MC96F6432S Series
Page 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...
Page 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...
Page 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...
Page 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...
Page 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...
