36
MC96F6432S
ABOV Semiconductor Co., Ltd.
7.14 Data Retention Voltage in Stop Mode
(T
A
=-40°C ~ +85°C, VDD=1.8V ~ 5.5V)
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
Data retention supply voltage
V
DDDR
–
1.8
–
5.5
V
Data retention supply current
I
DDDR
VDDR= 1.8V,
(T
A
= 25°C),
Stop mode
–
–
1
uA
Table 7.15
Data Retention Voltage in Stop Mode
Idle Mode
(Watchdog Timer Active)
V
DD
NOTE:
tWAIT is the same as (the selected bit overflow of BIT) X 1/(BIT Clock)
INT Request
Execution of
STOP Instruction
~ ~
Data Retention
~ ~
Stop Mode
Normal
Operating Mode
0.8V
DD
t
WAIT
V
DDDR
Figure 7.6
Stop Mode Release Timing when Initiated by an Interrupt
NOTE :
tWAIT is the same as (4096 X 4 X 1/fx) (16.4ms @ 1MHz)
VDD
RESETB
Execution of
STOP Instruction
~ ~
Data Retention
~ ~
Stop Mode
Oscillation
Stabillization Time
Normal
Operating Mode
TWAIT
RESET
Occurs
0.2 VDD
V
DDDR
0.8 VDD
Figure 7.7
Stop Mode Release Timing when Initiated by RESETB
Summary of Contents for MC96F6432S Series
Page 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...
Page 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...
Page 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...
Page 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...
Page 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...
