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MC96F6432S
ABOV Semiconductor Co., Ltd.
7.
1-Byte of data is being received.
8.
This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCLn LOW. When 1-
Byte of data is received completely, I2C generates TENDn interrupt.
I2C can choose one of the following cases according to the RXACKn flag in USInST2.
1) Master continues receiving data from slave. To do this, set ACKnEN bit in USInCR4 to ACKnowledge the
next data to be received.
2) Master wants to terminate data transfer when it receives next data by not generating ACK signal. This can
be done by clearing ACKnEN bit in USInCR4.
3) Because no ACK signal is detected, master terminates data transfer. In this case, set the STOPCn bit in
USInCR4.
4) No ACK signal is detected, and master transmits repeated START condition. In this case, load SLAn+R/W
into the USInDR and set the STARTCn bit in USInCR4.
After doing one of the actions above, clear to
“0b” all interrupt source bits in USInST2 to release SCLn line. In
case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In case of 4), move
to step 6 after transmitting the data in USInDR, and if transfer direction bit is
‘0’ go to master transmitter
section.
9.
This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that
data transfer between master and slave is over. To clear USInST2, write
“0” to USInST2. After this, I2C
enters idle state.
Summary of Contents for MC96F6432S Series
Page 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...
Page 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...
Page 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...
Page 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...
Page 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...
