Abov MC96F6432S Series, User Manual

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MC96F6432S ABOV Semiconductor Co., Ltd.
11.7.2 16-bit Timer/Counter Mode
The 16-bit timer/counter mode is selected by control register as shown in Figure 11.22.
The 16-bit timer have counter and data register. The counter register is increased by internal or timer 1 A match clock
input. Timer 2 can use the input clock with one of 1, 2, 4, 8, 32, 128, 512 and T1 A Match prescaler division rates
(T2CK[2:0]). When the values of T2CNTH/T2CNTL and T2ADRH/T2ADRLareidentical in timer 2, a match signal is
generated and the interrupt of Timer2occurs.The T2CNTH/T2CNTL valuesare automatically cleared by match signal.
It can be also cleared by software (T2CC).
T2MS[1:0]
T2POL
A Match
T2CC
T2EN
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/2
fx/4
fx/32
fx/128
fx/512
fx/8
fx/1
16-bit Counter
T2CNTH/T2CNTL
Clear
T1 A Match
Comparator
16-bit A Data Register
T2ADRH/T2ADRL
T2IFR
INT_ACK
Clear
To interrupt
block
A Match
Buffer Register A
Reload
Pulse
Generator
T2O
R
T2EN
3
T2CK[2:0]
2
A Match
T2CC
T2EN
T2EN
T2CRH
1
ADDRESS:C3H
INITIAL VALUE : 0000_0000B
–
T2MS1 T2MS0
– – –
T2CC
– 0 0 – – – X
T2CK2
T2CRL
X
ADDRESS:C2H
INITIAL VALUE : 0000_0000B
T2CK1 T2CK0 T2IFR
–
T2POL
–
T2CNTR
X X
X
–
X
–
X
NOTE)
1. T1 A Match is a pulse for the timer 2 clock source if it is selected.
Figure 11.22 16-bit Timer/Counter Mode for Timer 2