YOKOGAWA wt1600, Руководство пользователя

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6-2
IM 760101-11E
Overview of Registers and Queues
Name Function Writing Reading
Status byte — Serial poll (RQS) ,
*STB?(MSS)
Service request Masks status byte. *SRE *SRE?
enable register
Standard event Change in device — *ESR?
register status
Standard event Masks standard *ESE *ESE?
enable register event register
Extended event Change in device —
STATus:EESR?
register status
Extended event Masks standard STATus:EESE STATus:EESE?
enable register event register
Condition Current instrument status — STATus:
register
CONDition?
Transit Extended event STATus: STATus:
filter occurrence conditions FILTer<x> FILTer<x>?
Output queue Stores response message All executable queues
to a query.
Error queue Stores error Nos. — STATus:ERRor?
and messages.
Registers and Queues which Affect the Status Byte
Registers which affect each bit of the status byte are
shown below.
Standard event register : Sets bit 5 (ESB) of status
byte to “ 1 ” or “ 0 ”.
Output queue : Sets bit 4 (MAV) of status
byte to “ 1 ” or “ 0 ”.
Extended event register : Sets bit 3 (EES) of status
byte to “ 1 ” or “ 0 ”.
Error queue : Sets bit 2 (EAV) of status
byte to “ 1 ” or “ 0 ”.
Enable Registers
Registers which mask a bit so that the bit does not
affect the status byte, even if the bit is set to “ 1 ”, are
shown below.
Status byte : Masks bits using the service
request enable register.
Standard event register : Masks bits using the
standard event enable
register.
Extended event register : Masks bits using the
extended event enable
register.
Writing/Reading from Registers
The *ESE command is used to set bits in the standard
event enable register to “
1
” or “
0
”, and the
*ESR?
query is used to check whether bits in that register are
set to “
1
” or “
0
”. For details of these commands, refer
to Chapter 5.
6.2 Status Byte
Overview of Status Byte
7 6 ESB MAV EES EAV 1 0
RQS
MSS
Bits 0, 1 and 7
Not used (always “
0
”)
Bit 2 EAV (Error Available)
Set to “ 1 ” when the error queue is not empty, i.e. when
an error occurs. For details, refer to page 6-5.
Bit 3 EES (Extended Event Summary Bit)
Sets to “ 1 ” when the logical AND of an Extended Event
Register bit and the corresponding Enable Register bit
is equal to “ 1 .”—that is, when an event takes place in
the instrument. Refer to page 6-4.
Bit 4 MAV (Message Available)
Set to “ 1 ” when the output queue is not empty, i.e.
when there is data which is to be output when an query
is made. Refer to page 6-5.
Bit 5 ESB (Event Summary Bit)
Set to “
1
” when the logical AND of the standard event
register and the corresponding enable register is “ 1 ”,
i.e. when an event takes place in the instrument. Refer
to page 6-3.
Bit 6 RQS (Request Status)/MSS (Master Summary
Status)
Sets to “ 1 ” when the logical AND of any one of the
Status Byte bits (other than bit 6) and the
corresponding Service Request Enable Register bit
becomes “
1
”—that is, when the instrument is
requesting service from the controller.
RQS is set to “
1
” when MSS changes from “
0
” to “
1
”,
and is cleared when a serial poll is performed or when
MSS changes to “
0
”.
Bit Masking
To mask a bit in the status byte so that it does not
cause an SRQ, set the corresponding bit of the service
request enable register to “ 0 ”.
For example, to mask bit 2 (EAV) so that no service
will be requested, even if an error occurs, set bit 2 of
the service request enable register to “
0
”. This can be
done using the *SRE command. To query whether
each bit of the service request enable register is “
1
” or
“ 0 ”, use *SRE? . For details of the *SRE command,
refer to Chapter 5.
6.1 Overview of the Status Report/6.2 Status Byte