Themis USPIIi-1v, Руководство по оборудованию

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USPIIi-1v Hardware Manual
3-4
Themis Computer
3.2 System Specification
3.2.1 Processor & Memory Subsystems
Below are the processor and memory subsection specifications.
Table 3-1. Processor Specifications
Feature/Function Specifications
Processor UltraSPARC-IIi
Processor Speed Grade 1 - 360 MHz
Grade 2 - 440 MHz
Performance 18.3 SPECint95 @ 440 MHz w/ 2 MB cache (estimate)
20.4 SPECfp95 @ 440 MHz w/ 2 MB cache (estimate)
External Cache 2 MB SRAM, fast Register-Latch access mode
I/O Bus Interface 32 bit/66MHz PCI data path from CPU
Table 3-2. Memory Specification
Feature/Function Specifications
Main Memory Proprietary Coplanar Modules
One or Two Modules
a
a. Under certain conditions, it is actually possible to stack four memory modules for a total of 1 GBytes. Consult the factory.
Memory Bus Interface 72 bit Data Path from CPU, including 8 bit ECC
2 to 1 Interleave to DRAM
13 bit Address Bus
3.3V Level Interface
Memory Modules Four Module Types
64 MB, using 36 - 4Mx4 EDO DRAMs
128 MB, using 18 - 4Mx16 EDO DRAMs
256 MB, using 36 - 4Mx16 EDO DRAMs
512 MB, using 36 - 4Mx64 EDO DRAMs
Memory Configurations 64 MB - One 64 MB Module
128 MB - One 128 MB Module
256 MB - One 256 MB Module
512 MB - Two 256 MB Modules
512 MB - One 512 MB Module
1 GByte - Two 512 MB Modules