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USPIIi-1v Hardware Manual

7-4

Themis Computer

7.3.3

VMEbus Resets

A system reset from the VMEbus is received by the Universe IIB ASIC through the VME P1 connector. The
Universe IIB asserts LOCAL_RESET to the EPLD. The EPLD will de-assert POWER_OK to the RIC when
it receives LOCAL_RESET and initiate the same reset sequence as explained in the above section (refer to
Section 7.3.2, "Power Management Resets," on page 7-3).

An incoming VMEbus may be enabled or disabled through the setting of jumper JP3901. If JP3901 is
installed to 1-2 the USPII

i

-1v may be reset from the VMEbus. If JP3901 is installed to 2-3 or left open, resets

from the VMEbus will be disabled.

Outgoing VMEbus resets may also be enabled and disabled by setting jumper JP3801. If JP3801 is installed
to 1-2 a reset of the USPII

i

-1v will be propagated through the Universe IIB distributed through the VMEbus.

If JP3801 is installed to 2-3 or left open a reset of the USPII

i

-1v will not be propagated to the VMEbus.

Software may initiate a VMEbus Reset by writing to VME_Software_Reset address located at
0x1FF.F110.0001. A Software VMEbus Reset will reset only the VMEbus. No components on the USPII

i

-1v

are effected by a Software VMEbus Reset.

7.3.4

3-Level Watchdog Resets

A 3-Level Watchdog is implemented in the FPGA as explained in Section 6.1.3, "3-Level Watchdog," on
page 6-2. When the second watchdog in the FPGA expires, the FPGA asserts XIR to the RIC which
propagates the signal to the UltraSPARC-II

i

. This signal initiates an XIR in the processor. An XIR is not

propagated through the system. Only the processor is effected.

When the third watchdog in the FPGA expires, the FPGA assets POR to the RIC which propagates the signal
to the UltraSPARC-II

i

. This signal initiates a POR in the processor, which is propagated throughout the

system.

Note —

The 3-Level Watchdog is different from a Watchdog implemented internally on the UltraSPARC-

II

i

. Refer to Section 7.2.3, "Watchdog Reset (WDR)," on page 7-2 for more information concerning the

Watchdog Reset implemented internally on the UltraSPARC-II

i

.

7.3.5

Software POR

Software may initiate a reset equivalent to a Power-On-Reset (POR) by setting the SOFT_POR bit in the
UltraSPARC-II

i

Reset_Control Register (Table 7-1 ‘UltraSPARC-IIi Reset_Control Register,’ on page 7-5).

This bit will remain set until software clears it, to allow software to detect the source of the reset.

7.3.6

Software XIR

Software may initiate a reset equivalent to an Externally-Initiated-Reset (XIR) by setting the SOFT_XIR bit
in the UltraSPARC-II

i

Reset_Control Register (Table 7-1 ‘UltraSPARC-IIi Reset_Control Register,’ on page

7-5). This bit will remain set until software clears it, to allow software to detect the source of the reset.

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Содержание USPIIi-1v

Страница 1: ...USPIIi 1v Hardware Manual Revision B4...

Страница 2: ......

Страница 3: ...t Martin d H res France Phone 33 476 59 60 46 Fax 33 476 59 60 49 Themis Computer Americas and Pacific Rim 3185 Laurelview Court Fremont CA 94538 Phone 510 252 0870 Fax 510 490 5529 World Wide Web htt...

Страница 4: ...rior notice Themis Computer does not assume any liability arising from the application or use of this publication or the product s described herein RESTRICTED RIGHTS LEGEND Use duplication or disclosu...

Страница 5: ...A 2 page A 3 Reversed Serial Port C and D callouts pages C 3 C 4 and D 5 Version B3 October 5 2000 Corrected I O Board Jumper Setting references on page B 5 Version B2 July 20 2000 Changed definition...

Страница 6: ...USPIIi 1v User s Manual Themis Computer...

Страница 7: ...3 Backplane Jumper Settings 2 2 2 4 Installing The USPIIi 1v Paddle Board 2 3 2 5 Attaching Cables to Peripheral Devices 2 4 2 5 1 Console Port TTYA 2 4 2 5 2 Keyboard and Mouse 2 5 2 5 3 Ethernet Net...

Страница 8: ...Memory Subsystem 4 4 4 3 PMC Carrier Subsystem 4 5 4 4 OpenBoot PROM 4 5 5 Universe IIB Description 5 1 5 1 Features 5 1 5 2 USPIIi 1v and the Universe IIB PCI Interface 5 2 5 3 VMEbus Interface 5 2...

Страница 9: ...7 2 7 2 2 Externally Initiated Reset XIR 7 2 7 2 3 Watchdog Reset WDR 7 2 7 2 4 Software Initiated Reset SIR 7 3 7 3 Reset Sources 7 3 7 3 1 Push Button Reset 7 3 7 3 2 Power Management Resets 7 3 7...

Страница 10: ...2 32 Bit User I O Configuration A 27 A 5 Paddle Board A 28 A 5 1 SCSI Connector A 28 A 5 2 MII Connector A 30 A 5 3 DB9 Connector A 31 B Jumper and Solder Bead Configurations B 1 B 1 Overview B 1 B 2...

Страница 11: ...ess 0 Register PCI_BS0 5 7 Table 5 5 PCI Configuration Base Address 1 Register PCI_BS1 5 7 Table 5 6 VMEbus Fields for VMEbus Slave Image 5 8 Table 5 7 PCI Bus Fields for VMEbus Slave Image 5 8 Table...

Страница 12: ...colors of the ALARM LED A 13 Table A 11 I O Board VME P2 Connector A 14 Table A 12 I O Board TTY C AND TTY D Pinout A 16 Table A 13 I O Board Parallel Port Pinout A 18 Table A 14 RJ45 Ethernet B Pinou...

Страница 13: ...e A 5 Baseboard Console and Keyboard Mouse Connector Orientation PS 2 Mode A 9 Figure A 6 PS 2 Keyboard Mouse Split Cable A 10 Figure A 7 Serial Port Adapter Cable A 11 Figure A 8 Baseboard Console an...

Страница 14: ...Solder Beads B 10 Figure C 1 Single Slot Front Panel C 2 Figure C 2 Double Slot Front Panels C 3 Figure C 3 Triple Slot Front Panel C 4 Figure D 1 Baseboard Front Panel Diagram D 2 Figure D 2 Baseboa...

Страница 15: ...ritten for system integrators and programmers It contains all necessary information for installation and configuration of the USPIIi 1v and assumes the Open Boot Program OBP code is installed in the s...

Страница 16: ...static measures must be observed when removing the USPIIi 1v from its shipping container and during any subsequent handling A wrist strap or grounding strap provides grounding for static electricity b...

Страница 17: ...er Cables for Serial Ports C or D Themis Part Number 108376 A 26 pin Male Amplimite connector to DB25 printer cable for the Parallel Port Themis Part Number 104077 Please report any discrepancies to T...

Страница 18: ...Watchdog Voltage and Temperature Sensors provides a description of the FPGA and EPLD on the USPIIi 1v Included in this chapter are description of the temperature warning system boot address decoder po...

Страница 19: ...1998 Rev A Integrated Circuit Specifications UltraSPARC IIi User s Manual SUN Part Number 805 0087 01 SME1040 Highly Integrated 64 bit RISC Processor PCI Interface Data Sheet SUN Part Number 805 0086...

Страница 20: ...USPIIi 1v Hardware Manual 1 6 Themis Computer...

Страница 21: ...use PS 2 type keyboard and mouse Sun configuration means that Sun type 5 keyboard and mouse can be installed USPIIi 1v and 1v 2p boards are only available in PS 2 mode To determine the mode configure...

Страница 22: ...t C and D as RS232 All other I O board jumpers are left uninstalled PMC Carrier Board J11 and J12 the User I O Adapter Card is left uninstalled This will route all 64 bits of User I O on the PMC Carri...

Страница 23: ...nstalled at the rear of the P2 backplane behind the position occupied by the baseboard for the USPIIi 1v 2p a second VME slot is occupied by the PMC extension carrier The paddle board provides connect...

Страница 24: ...ll modem and a gender changer may be required for attachment to your serial terminal or emulator Note If the USPIIi 1v is used with Creator Graphics it is not mandatory to attach it to a serial termin...

Страница 25: ...ou can verify proper physical connection by executing the Openboot network selftest test net This test will indicate external loopback failure on each of the network interfaces when there is not a pro...

Страница 26: ...raphics must be used in conjunction with a PS 2 or Sun keyboard and mouse If the latter are not attached to the USPIIi 1v board prior to power on OpenBoot will redirect its text output to the serial c...

Страница 27: ...ional It is also possible to have the Baseboard with Creator Graphics without the I O board or the Baseboard with the I O Board but without Creator Graphics card These options are also possible with t...

Страница 28: ...e out Also rear access is provided on the P2 connector for Ethernet B MII SCSI B and Serial ports C or D 3 1 3 PMC Carrier Board A PMC Carrier Board is available for vendor specific 32 bit 33 MHz PMC...

Страница 29: ...ps EDO DRAM chips Addr 144 PCI VME 66MHz 32 bit PCI SCSI Ethernet A Super I O TOD Flash E Bus Serial Keyboard Parallel RIC PCIOs f f f f b b f 33MHz APB Cards Cache Interface f B A A b Bridge PMC Expa...

Страница 30: ...PU Table 3 2 Memory Specification Feature Function Specifications Main Memory Proprietary Coplanar Modules One or Two Modulesa a Under certain conditions it is actually possible to stack four memory m...

Страница 31: ...lot 1 P2b Slot 1 P2b Slot 1 P2b Slot 1 P2b Serial Port C Asynchronous Synchronous RS 232 422 na Slot 2 FP P2c na Slot 2 FP P2c Serial Port D Asynchronous Synchronous RS232 422 na Slot 2 FP P2c na Slot...

Страница 32: ...available on P2 c Selection is exclusive Only one between ports C and D is available on P2 d The User I O on the PMC Carrier Board may be configured Either 64 bits of User I O may be made available o...

Страница 33: ...hen outside of 4 75 5 25 V POR when outside of 4 5V 5 5 V Temperature Sensors Two Level Level One XIR Level Two Shutdown Table 3 5 USPIIi 1v Operating Environmental Specifications Description Minimum...

Страница 34: ...r 3 4 Estimated Power Requirements Table 3 7 Estimated Power Requirements Configuration USPIIi 1v 1 with 360 440 MHz processor Watts Dissipation typical 128 MBytes memory 32 34 Watts 256 MBytes memory...

Страница 35: ...storage and error management the operating system requires no knowledge of the E Cache after initialization The E Cache includes the content of the Instruction Cache I Cache and the Data Cache D Cache...

Страница 36: ...hese functions are divided into independent functional blocks on the RIC The interrupt controller on the RIC accepts all interrupts from the USPIIi 1v subsystems up to 41 interrupts and delivers encod...

Страница 37: ...A implements a voltage monitor boot address decoder a three level watchdog timer and the SYSTEM_OK_LED register At boot up the FPGA self loads from a serial EPROM Altera EPC1213PC8 to program itself f...

Страница 38: ...y of one 1 second per day NVRAM and TOD are programmed using the FORTH toolkit in Open Boot Program OBP 4 2 Memory Subsystem The USPIIi 1v supports up to two coplanar memory modules of either 64 MB 12...

Страница 39: ...se PMC 1 will utilize the upper VME P2 signals VME P2 A 32 17 and VME P2 C 32 17 while PMC 2 will utilize the lower VME P2 signals VME P2 A 16 1 and VME P2 C 16 1 The signals are available on the J5 c...

Страница 40: ...itor is signified by the ok prompt If a boot attempt fails the OBP tries to start the abbreviated system monitor Supplies program code for the FORTH Toolkit the on board diagnostics contain the FORTH...

Страница 41: ...lave transfer except for A64 and A40 D64 D32 D16 D08 master and slave transfer except for MD32 MBLT BLT ADOH RMW LOCK and location monitors Support for full VMEbus System Controller Nine user programm...

Страница 42: ...the Universe II cannot reflect a cycle on the VMEbus and access itself as it is capable of doing so Depending on the programmed values of the VMEbus slave images the incoming write transaction from th...

Страница 43: ...e the PCI Master Interface to issue an interrupt The Universe IIB supports the VMEbus lock commands as they are described in the VME64 Specification The ADOH cycles are used to execute the lock comman...

Страница 44: ...he Universe IIB samples the BG3IN right after the reset to determine if the USPIIi 1v resides in slot 1 If the BG3IN is sampled low right after the reset the USPIIi 1v board becomes the SYSCON Otherwi...

Страница 45: ...pecification Proprietary Method which is developed by Tundra 25 24 VARBTO VMEbus Arbitration Time out 00 Disable Timer 01 16 s minimum value of 8 s due to the 8 s clock granularity 10 256 s others RES...

Страница 46: ...p options on the USPIIi 1v The Universe IIB is automatically configured at power up to operate in the default configuration listed in Table 5 3 Universe IIB Power Up Options on page 5 6 It should be n...

Страница 47: ...1 PCI Bus Sizec MISC_STAT LCLSIZE 32 bit REQ64 PCI CSR Image Size PCI_CSR BM disabled VA 14 a The LAS field will enable the PCI_CSR registers IOS or MS field if the EN FIELD of the LSIO_CTL register...

Страница 48: ...The Universe II s eight VMEbus slave images 0 7 are bounded by A32 space Slave images 0 and 5 have a 4 KB resolution Typically these images would be used as an A16 image since they provided the fines...

Страница 49: ...CI target images that open windows to the VMEbus and control to the type of access to the VMEbus There are eight 0 7 standard PCI target images and one special PCI target image The special PCI target...

Страница 50: ...image must not overlap with the address space for the Universe II s control and status registers 5 4 2 2 VMEbus Fields The VMEbus fields cause the Universe II to generate the appropriate VMEbus addres...

Страница 51: ...pically programmed to access A32 space The special PCI target image is a 64 MB space located either within memory or I O space that is decoded using PCI address lines 31 26 Its base address is aligned...

Страница 52: ...Image Field Register Bits Description maximum data width VDW in separately set each region for 16 or 32 bits mode SUPER in separately set each region for supervisor or non privileged type PGM in Prog...

Страница 53: ...0 Supervisor User AM Code Each of the four bits specifies Supervisor User AM code for the corresponding 16 MB region Lower order bits correspond to the lower address regions 0 Non Privileged 1 Supervi...

Страница 54: ...the software source always has higher priority Interrupt sources mapped to the PCI bus interrupts are generated via the PCI Interrupt pin INT 0 For the VMEbus interrupt outputs the Universe IIB interr...

Страница 55: ...obtain the ownership of a semaphore a processor writes a logic one to the semaphore bit and an unique pattern to the associated tag field if a subsequent read of the tag field returns the same patter...

Страница 56: ...irect Mode In Linked List Mode the Universe IIB loads the DMA registers from PCI memory and executes the transfers described by these registers In the direct mode the PCI master directly programs the...

Страница 57: ...ures Full description of the FPGA registers is presented in the USPIIi 1v Software Manual 6 1 2 Boot Address Decoder The Flash EPROM logic is made of 3 Flash devices System Flash 2MB or 4 MB is loaded...

Страница 58: ...Registers Note The 3 level watchdog implemented in the FPGA is entirely separate from the internal watchdog of the UltraSPARC IIi For more information on the watchdog implemented in the UltraSPARC II...

Страница 59: ...nitial programmed states The entire 3 Level Watchdog may be disable through the setting of solder bead SB3302 When solder bead SB3302 is installed shorted the watchdog is enabled When solder bead SB33...

Страница 60: ...coping state will turn the front ALARM LED to amber In failed state the LED will turn RED and the POWER FAIL signal will be asserted on VME P2 See Appendix A 2 2 Baseboard VME P2 and Appendix A 2 9 L...

Страница 61: ...mp warning and temp critical These variables may be configured by through OBP extension variables refer to the USPIIi 1v Software Manual The settings of temp critical and temp warning are stored in th...

Страница 62: ...USPIIi 1v Hardware Manual 6 6 Themis Computer...

Страница 63: ...ED_state consult Section 17 3 RED_state of the UltraSPARC IIi User s Manual The USPIIi 1v reset tree uses the UltraSPARC IIi CPU in conjunction with the SME Reset Interrupt and Clock chip RIC an FPGA...

Страница 64: ...riorities from highest to lowest are POR XIR WDR and SIR 7 2 1 Power On Reset POR A POR is a processor and board reset When POR is active all other resets and traps are ignored Any pending external tr...

Страница 65: ...3 2 Power Management Resets on page 7 3 7 3 1 Push Button Reset The Push Button Reset is one of the three ways the UltraSPARC IIi may receive a POR Push Button Reset in activated by pressing the push...

Страница 66: ...is implemented in the FPGA as explained in Section 6 1 3 3 Level Watchdog on page 6 2 When the second watchdog in the FPGA expires the FPGA asserts XIR to the RIC which propagates the signal to the Ul...

Страница 67: ...0 Reserved R0 POR 31 a a The highest priority reset source has its bit set Only the bits marked with are set Set if the last reset was due to the assertion of SYS_RESET_L R W1C SOFT_POR 30 Setting to...

Страница 68: ...oftware Initiated Reset SIR These two resets are initiated within the processor core and effect only the processor VME FPGA RIC UltraSPARC IIi APB X2 5V X3 3V X5 0V CONF_DONE Button_XIR_L Button_POR E...

Страница 69: ...I O Board PMC Carrier Board and Paddle Board connector pinouts are each presented as individual sections For a diagram of the front panel I O available on each board refer to Appendix C Front Panel Di...

Страница 70: ...VME SYSFAIL 11 GND VME BGOUT3 VME BERR 12 VME DS1 VME BR0 VME SYSRESET 13 VME DS0 VME BR1 VME WORD 14 VME WRITE VME BR2 VME AM5 15 GND VME BR3 VME A23 16 VME DTACK VME AM0 VME A22 17 GND VME AM1 VME A...

Страница 71: ...efer to 6 1 4 Power Management System on page 6 3 or when VME ACFAIL is active HI TEMP Asserted when Critical Temperature is reached refer to 6 2 Temperature Sensor on page 6 5 SW ALARM User defined A...

Страница 72: ...Datac VME D25 SCSI A DAT 10 25 Serial B DCD or PS 2 KB CLKc VME D26 SCSI A DAT 11 26 Serial B DSR or PS 2 VCC FILc VME D27 SCSI A DAT 12 27 Serial B RI or PS 2 MSCLKc VME D28 SCSI A DAT 13 28 HI TEMP...

Страница 73: ...MII A TXD1 VME D17 SCSI A DAT 2 16 MII A TXD2 VME D18 SCSI A DAT 3 17 MII A TXD3 VME D19 SCSI A DAT 4 18 MII A COL VME D20 SCSI A DAT 5 19 MII A CRS VME D21 SCSI A DAT 6 20 Sun KB Out VME D22 SCSI A D...

Страница 74: ...SCSI A and B Pinout Pin Signal Name Pin Signal Name 1 GND 35 DAT 12 2 GND 36 DAT 13 3 GND 37 DAT 14 4 GND 38 DAT 15 5 GND 39 PAR 1 6 GND 40 DAT 0 7 GND 41 DAT 1 8 GND 42 DAT 2 9 GND 43 DAT 3 10 GND 4...

Страница 75: ...EQ 30 GND 64 IO 31 GND 65 DAT 8 32 GND 66 DAT 9 33 GND 67 DAT 10 34 GND 68 DAT 11 a This is part of the Automatic SCSI termination logic The SCSI FP signal will be forced to ground by the mating SCSI...

Страница 76: ...mputer A 2 4 RJ45 Ethernet A Connector Connector Type RJ 45 TPE Figure A 4 Ethernet A Connector Orientation Table A 5 RJ45 Ethernet A Pinout Pin Signal Name 1 TXD 2 TXD 3 RXD 4 4T_D3P 5 4T_D3P 6 RXD 7...

Страница 77: ...ure A 5 Baseboard Console and Keyboard Mouse Connector Orientation PS 2 Mode Table A 6 Baseboard Console and Keyboard Mouse Pinout PS 2 Mode Pins Keyboard Mouse Signal Names Pins Serial Port A Signal...

Страница 78: ...ra a Pins 2 and 6 of the Keyboard Connector are No Connects PS 2 Mouse Pin Numberb b Pins 2 and 6 of the PS 2 Mouse Connector are No Connects 1 KB DATA Keyboard Pin 1 NC 2 NC NC NC 3 GND Keyboard Pin...

Страница 79: ...er Cable Table A 8 Serial Port A Console Adapter Cable Front Panel Serial Port A Console Pinout Signal Name Serial Port A Cable Pinouta a All unlisted pins on the DB25 connector are No Connect Miniatu...

Страница 80: ...console TTYA port through a cable available from Themis Micro SUB DB9 to DIN8 Part Number is 108783 Connector Type Two 2 stacked Mini DB9 Part Number ITT Cannon MDSM 18PE Z10 VR25 Figure A 8 Baseboar...

Страница 81: ...sh is corrupted or the board is damaged A 2 10 Push Button RESET A push button RESET is located on the front panel of the baseboard This button will initiate a POR Reset to the UltraSPARC IIi This res...

Страница 82: ...ion between serial port C and D signals on P2 is made by solder beads SB0301 to SB0306 Refer to Section Figure B 5 I O Board Solder Side Solder Beads on page B 10 Connector Type VME32 Figure A 9 I O B...

Страница 83: ...rial C D RTS VME D24 SCSI B DAT 9 24 Serial C D DTR VME D25 SCSI B DAT 10 25 Serial C D DCD VME D26 SCSI B DAT 11 26 Serial C D DSR VME D27 SCSI B DAT 12 27 Serial C D RI VME D28 SCSI B DAT 13 28 NC V...

Страница 84: ...means of jumpers JP0705 JP0706 JP0801 JP0808 Default setting is RS232 Also they can be set to synchronous mode by means of jumpers JP0703 0704 Default is asynchronous See Appendix Table B 2 I O Board...

Страница 85: ...NC 13 CTS 39 CTS 14 TXD 40 TXD 15 NC 41 NC 16 RXD 42 RXD 17 RXC 43 RXC 18 NC 44 NC 19 RTS 45 RTS 20 DTR 46 DTR 21 NC 47 NC 22 NC 48 NC 23 DTR 49 DTR 24 TXC 50 TXC 25 NC 51 NC 26 NC 52 NC Table A 12 I...

Страница 86: ...823 1 Figure A 11 I O Board Parallel Port Connector Orientation Table A 13 I O Board Parallel Port Pinout Pins Signal Name Pins Signal Name 1 ACK 14 STRB 2 BUSY 15 GND 3 AFXN 16 GND 4 INIT 17 GND 5 SL...

Страница 87: ...0B A 3 6 Creator Graphics Slot With the USPIIi 1v 2c and 1v 3 a Creator Graphics Card may be installed on the baseboard UPA64S connector J4901 The card will occupy the second slot adjacent to the I O...

Страница 88: ...ector Type VME32 Figure A 13 PMC Carrier Board VME P1 Connector Orientation Table A 15 PMC Carrier Board VME P1 Pinout Pin Row A Signal Name Row B Signal Name Row C Signal Name 1 NC NC NC 2 NC NC NC 3...

Страница 89: ...GND NC 21 DAISY_CHAIN_IACK NC NC 22 DAISY_CHAIN_IACK NC NC 23 NC GND NC 24 NC NC NC 25 NC NC NC 26 NC NC NC 27 NC NC NC 28 NC NC NC 29 NC NC NC 30 NC NC NC 31 12V NC 12V 32 VCC VCC VCC Table A 15 PMC...

Страница 90: ...ame 1 PMC IO A1 VCC PMC IO C1 2 PMC IO A2 GND PMC IO C2 3 PMC IO A3 NC PMC IO C3 4 PMC IO A4 NC PMC IO C4 5 PMC IO A5 NC PMC IO C5 6 PMC IO A6 NC PMC IO C6 7 PMC IO A7 NC PMC IO C7 8 PMC IO A8 NC PMC...

Страница 91: ...4 25 PMC IO A25 NC PMC IO C25 26 PMC IO A26 NC PMC IO C26 27 PMC IO A27 NC PMC IO C27 28 PMC IO A28 NC PMC IO C28 29 PMC IO A29 NC PMC IO C29 30 PMC IO A30 NC PMC IO C30 31 PMC IO A31 GND PMC IO C31 3...

Страница 92: ...and J12 Consult the factory Both PMC Carrier Slot 1 and Slot 2 use the connector type illustrated in Figure A 15 PMC Carrier Board User I O Connector Connector Type 64 Pin Female 10mm Dual Row Connect...

Страница 93: ...A26 21 PMC IO C11 53 PMC IO C27 22 PMC IO A11 54 PMC IO A27 23 PMC IO C12 55 PMC IO C28 24 PMC IO A12 56 PMC IO A28 25 PMC IO C13 57 PMC IO C29 26 PMC IO A13 58 PMC IO A29 27 PMC IO C14 59 PMC IO C30...

Страница 94: ...39 PMC IO C20 8 NC 40 PMC IO A20 9 NC 41 PMC IO C21 10 NC 42 PMC IO A21 11 NC 43 PMC IO C22 12 NC 44 PMC IO A22 13 NC 45 PMC IO C23 14 NC 46 PMC IO A23 15 NC 47 PMC IO C24 16 NC 48 PMC IO A24 17 NC 4...

Страница 95: ...NC 7 PMC IO C4 39 NC 8 PMC IO A4 40 NC 9 PMC IO C5 41 NC 10 PMC IO A5 42 NC 11 PMC IO C6 43 NC 12 PMC IO A6 44 NC 13 PMC IO C7 45 NC 14 PMC IO A7 46 NC 15 PMC IO C8 47 NC 16 PMC IO A8 48 NC 17 PMC IO...

Страница 96: ...onnector Table A 20 Paddle Board SCSI Connector Pinout Pin Signal Name Pin Signal Name 1 GND 35 DAT12 2 GND 36 DAT13 3 GND 37 DAT14 4 GND 38 DAT15 5 GND 39 PAR1 6 GND 40 DAT0 7 GND 41 DAT1 8 GND 42 DA...

Страница 97: ...D 29 GND 63 REQ 30 GND 64 IO 31 GND 65 DAT8 32 GND 66 DAT9 33 GND 67 DAT10 34 GND 68 DAT11 a This is part of the Automatic SCSI termination logic SCSI P2 signal will be forced to ground by the mating...

Страница 98: ...Signal Name Pin Signal Name 1 VCC 21 VCC 2 MII_MDIO 22 GND 3 MII_MDC 23 GND 4 MII_RXD3 24 GND 5 MII_RXD2 25 GND 6 MII_RXD1 26 GND 7 MII_RXD0 27 GND 8 MII_RX_DV 28 GND 9 MII_RX_CLK 29 GND 10 MII_RX_ER...

Страница 99: ...Right Angel DB9 Connector Part Number AMP 747840 4 Figure A 18 Paddle Board DB9 Connector Table A 22 Paddle Board DB9 Connector Pinout Pin Signal name in serial mode Signal name in PS 2 mode Signal n...

Страница 100: ...USPIIi 1v Hardware Manual A 32 Themis Computer...

Страница 101: ...ld seriously damage the USPIIi 1v DO NOT ATTEMPT TO ALTER SOLDER BEAD CONFIGURATIONS B 2 Field Configurables B 2 1 Baseboard Jumpers Table B 1 Baseboard Jumper Setting Jumper Position Description JP14...

Страница 102: ...04 1 2 Boot the OBP from the User Flash 2 3 Boot the OBP from the System Flash ROMBO 2 3 is the same as the default The default is Uninstalled JP3801 1 2 Enables the USPIIi 1v s assertion of SYSRESET_...

Страница 103: ...mper Locations JP3302 JP3303 JP4902 JP3301 JP1401 JP1601 JP3801 J1501 JP3304 1 2 7 8 JP4901 JP1502 JP3901 JP4201 USPIIi 1V DEFAULT JUMPERS INSTALLED JP1401 1 2 JP1601 2 3 JP3801 1 2 JP3901 1 2 All oth...

Страница 104: ...rt D is Asynchronous Default Short Installed Serial Port D is Synchronous JP0705 Open Serial Port C is RS422 Short Installed Serial Port C is RS232 Default JP0706 Open Serial Port D is RS422 Short Ins...

Страница 105: ...Themis Computer B 5 B Jumper and Solder Bead Configurations Figure B 2 I O Board Jumper Locations...

Страница 106: ...connector On P2 serial port B or PS 2 keyboard mouse signals depending on SB1806 1811 2 3 Defines Sun configuration Sun keyboard mouse signals on front panel CONSOLE connector and on P2 SB1806 to 1811...

Страница 107: ...Solder Side Solder Bead Locations on page B 9 provide the location of the baseboard solder beads SB3304 1 2 5 V to FLASH Default 2 3 12 V to FLASH SB3305 1 2 5 V to FLASH Default 2 3 12 V to FLASH SB...

Страница 108: ...USPIIi 1v Hardware Manual B 8 Themis Computer Figure B 3 Baseboard Component Side Solder Bead Locations SB3302 SB2401 SB3202...

Страница 109: ...r and Solder Bead Configurations Figure B 4 Baseboard Solder Side Solder Bead Locations SB3305 SB3304 SB1401 SB3303 SB3203 1 1 1 3 3 3 SB3301 SB3501 SB3502 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 SB1808 SB180...

Страница 110: ...er Beads B 3 3 PMC Carrier Board Solder Beads There are no solder beads on the PMC Carrier Board Table B 5 I O Board Solder Side Solder Beads Solder Bead Setting Description SB0301 0306 1 2 Serial Por...

Страница 111: ...rontPanelDiagrams C 1 Introduction The following sections present diagrams of the front panels for all possible configurations of the USPIIi 1v It is intended as a quick reference for the front panel...

Страница 112: ...er C 2 Baseboard Front Panel Figure C 1 Single Slot Front Panel CONSOLE TTYA PS 2 KEYBOARD MOUSE SCSI PORT A SCSI PORT B POWER_OK_LED SYSTEM_OK_LED PUSH BUTTON RESET EJECTOR RJ45 ALARM READY RESET USP...

Страница 113: ...TON RESET EJECTOR RJ45 ALARM READY RESET USPIIi 1v 2p TRIPLE PMC EXPANSION CONFIGURATION EJECTOR PMC SLOT 2 PMC SLOT 1 PMC SLOT 3 SUN KB MS or CONSOLE PS 2 KEYBOARD MOUSE SCSI PORT A SCSI PORT B POWER...

Страница 114: ...SLOT 2 PMC SLOT 1 PMC SLOT 3 SUN KB MS or CONSOLE PS 2 KEYBOARD MOUSE SCSI PORT A SCSI PORT B POWER_OK_LED SYSTEM_OK_LED PUSH BUTTON RESET EJECTOR RJ45 ALARM READY RESET USPIIi 1v 3 BASEBOARD GRAPHIC...

Страница 115: ...Themis Computer D 1 D DBoardDiagrams D 1 Baseboard Board Diagrams...

Страница 116: ...ter Figure D 1 Baseboard Front Panel Diagram Ethernet A RJ45 TPE Connector Keyboard Mouse Connector Upper from PCB Serial Port A Connector Lower from PCB SCSI B Upper from PCB SCSI A Lower from PCB Po...

Страница 117: ...raSPARC IIi SME2411 Advance PCI Bridge SME STP2210 Reset Interrupt and Clock National Super I O PC87307ICEVUL Symbios SYM53C876 SCSI Controller SME STP2003 PCI I O Controller Tundra Universe II VME to...

Страница 118: ...USPIIi 1v Hardware Manual D 4 Themis Computer Figure D 3 Baseboard Connector Diagram Memory Card Connectors Expanded I O Connector Creator Graphics PMC Carrier Board UPA Connector...

Страница 119: ...I O Board Diagrams Figure D 4 I O Board Component Side Line in Line Out Ethernet B TTY C Upper Connector TTY D Lower Connector Parallel Siemens 82532 UART SME STP2003 CHEERIO VME P2 Connector PMC Carr...

Страница 120: ...ware Manual D 6 Themis Computer D 3 PMC Board Figure D 5 PMC Carrier Board Component Side J9 J10 J6 J7 J8 J11 J12 J3 J4 J5 Digital 21150 Bridge User I O Adapter Connectors PMC Carrier 3 PMC Carrier 2...

Страница 121: ...rams Figure D 6 PMC Board Connector Diagram J9 J10 J6 J7 J8 J11 J12 J3 J4 J5 Digital 21150 Bridge User I O Adapter Board Connectors PMC 1 User I O Connector PMC 1 Connectors PMC 2 Connectors PMC 3 Con...

Страница 122: ...v Hardware Manual D 8 Themis Computer D 4 Paddle Board Figure D 7 Paddle Board Component Side VME P2 Serial Port B DB 9 AMP 787170 4 MII Ethernet Miniature DB40 AMP 787082 7 SCSI A Miniature DB68 AMP...

Страница 123: ...hardware to execute and run an operating System such as Solaris 2 6 CPCI Compact PCI An adaptation of the PCI Specification for industrial and or embedded applications requiring a more robust mechanic...

Страница 124: ...ical memory or I O device space PIO Accesses by a Master on the primary bus to a Slave on the secondary bus PIO is equivalent to Downstream Probing A process implemented in the firmware and software t...

Страница 125: ...essor that maps all system wide program visible memory Virtual addresses usually are translated by a combination of hardware and software to physical addresses which can be used to access physical mem...

Страница 126: ...USPIIi 1v Hardware Manual E 4 Themis Computer...

Страница 127: ...ThemisComputer 3185LaurelviewCourt Fremont CA94538 Attn PublicationsDepartment Place Stamp Here...

Страница 128: ...ble___ The manuals were useful Agree___ Disagree___ Not Applicable___ Please write down any additional comments you may have about these manuals _______________________________________________________...

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