Themis USPIIi-1v, Руководство по оборудованию

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Themis Computer
6-3
6. FPGA, Watchdog, Voltage and Temperature Sensors
When no watchdogs have expired the USPII i -1v is in a ‘normal’ state. When the level 1 watchdog expires, a
maskable interrupt is sent to the RIC. The USPII i -1v is considered to be in a ‘warning’ state. Upon expiration,
the level 2 watchdog issues a non-maskable XIR interrupt to the RIC. This signal has the same effect as an
“Abort” button assertion and will terminate the active job. When this occurs the board is considered to be in
a ‘coping’ state.
The level 3 watchdog causes a “serious alarm condition” when it expires. The USPII i -1v is then considered to
be in a ‘failed’ state. This signal is connected to the backplane of the board. This signal will generate a non-
maskable Power-On-Reset to be issued to the UltraSPARC-II
i and propagated throughout the system. This
reset may be disabled by setting jumper J3301. If jumper J3301 is set to 1-2 the reset is enabled. If jumper
J3301 is set to 2-3 the reset is disabled.
Expiration of watchdog level 2 will turn the front panel ALARM LED to amber. Expiration of watchdog level
3 will turn it to red and cause the assertion of the SW ALARM pin on VME P2. See Appendix A.2.2,
"Baseboard VME P2," and Appendix A.2.9, "LEDs."
Upon expiration, any higher-order watchdog will reset a lower-order watchdog, i.e.: the expiration of
watchdog 3 resets watchdog 1 and watchdog 2 to their initial, programmed states.
The entire 3-Level Watchdog may be disable through the setting of solder bead SB3302. When solder bead
SB3302 is installed (shorted) the watchdog is enabled. When solder bead SB3302 is open, the watchdog is
disabled.
6.1.4 Power Management System
A voltage monitor is implemented in the FPGA and with external circuitry. The USPII i -1v voltage monitor
has three states: normal, coping, and failed. The +5V, +3.3V and +1.9V signals are monitored for drops of -
5% and -10%. The voltage monitor is in a normal state if all three voltage levels are within 5% of nominal.
The voltage monitor is in a coping state if any of the signals drop below -5%. If the voltage monitor is in the
coping state for longer than 100 milliseconds, the FPGA will generate an XIR interrupt to the RIC. If the
voltage monitor is in the coping state for longer than 500 milliseconds, the ‘Functional Bit’ of the FPGA
status register is set.
If a voltage drop of more than -10% for more than 100 milliseconds is detected the board will enter the
‘failed’ state. When entering the failed state the USPII
i -1v’s FPGA will shut down both the 3.3V and the 1.9V
DC-DC power converters, in order to protect the board from damage. It is necessary to cycle the power in
order to recover from this type of shutdown.
Table 6-4. Watchdog POR Enable/Disable
Jumper J3301 Setting Description
Installed 1-2 or Not installed (Default) Disable Reset
Installed 2-3 Enable Reset
Table 6-5. Watchdog Enable/Disable
Solder Bead SB3302 Setting Description
Installed 3-Level Watchdog Enabled
Open (Default) 3-Level Watchdog Disabled