Themis USPIIi-1v, Руководство по оборудованию

Страница: 65 / 128

Themis Computer
7-3
7. Resets
Note that a WDR reset initiated internal to the processor is different that the 3-Level Watchdog implemented
in the FPGA of the USPII
i -1v. For further explanation of the 3-Level Watchdog Section 7.3.4, "3-Level
Watchdog Resets," on page 7-4.
7.2.4 Software Initiated Reset (SIR)
A Software Initiated Reset is initiated by an SIR instruction from supervisory software. It is initiated within
the UltraSPARC-II
i core and effects only the UltraSPARC-II i . An SIR is not propagated to the I/O or external
system.
7.3 Reset Sources
The UltraSPARC-II i accepts two reset signals from the RIC: POR_Reset, and XIR_Reset. The RIC receives
reset signals from the FPGA. The RIC accepts to five resets from the system: Power_OK, Push_Button_POR,
Push_Button_XIR, Scan_POR, and Scan_XIR. Scan_POR and Scan_XIR are used for engineering test
purposes only and not used during the normal operation of the board. POWER_OK is propagated from the
FPGA, through the EPLD, to the RIC. The RIC interprets these signals and issues an appropriate signal, as
explained in succeeding sections.
The UltraSPARC-II i also accepts SYS_RESET_L from the FPGA. Part of the power management system,
this signal will cause a reset of the USPII i -1v, as explained below (refer to Section 7.3.2, "Power Management
Resets," on page 7-3).
7.3.1 Push Button Reset
The Push Button Reset is one of the three ways the UltraSPARC-II i may receive a POR. Push Button Reset
in activated by pressing the push button on the front panel of the USPII i -1v. This activates the
Push_Button_POR to the RIC. The RIC propagates the signal as a POR to the UltraSPARC-II i which will
reset the processor. When a Push Button reset in initiated, the B_POR in the Reset_Control_Register (Table
7-1 ‘UltraSPARC-IIi Reset_Control Register,’ on page 7-5) will be set until software clears it. This is done to
allow software to detect the source of the reset. The POR bit will not be set.
7.3.2 Power Management Resets
The power management system on the USPII i -1v is the second source of a POR for the UltraSPARC-II i . The
power management system will detect if any of the voltage signals (2.5V, 3.3V, or 5V) drop below 10% of
their specified values. If such a situation occurs the FPGA, where the decision logic of the power management
system is implemented, will assert FPGA_POWER_OK to the EPLD which then asserts POWER_OK to the
RIC. The RIC will assert SYS_RST_PAL to the FPGA which then asserts SYS_RESET_L to the
UltraSPARC-II
i . The UltraSPARC-II i receives this signal as a POR and propagates a reset throughout the
USPII i -1v. This sequence occurs during board power-up. The USPII i -1v will maintain a reset state until all
system voltages are with nominal values and the FPGA is fully configured.