Themis USPIIi-1v, Руководство по оборудованию

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USPIIi-1v Hardware Manual
5-8
Themis Computer
5.4.1 VME Slave Images
A VMEbus slave image is used to access the resources of the PCI bus when the Universe II is not the
VMEbus master. The user may control the type of accesses by programming specific attributes of the
VMEbus slave image. The Universe II will only accept accesses to the VMEbus from with the programmed
limits of the VMEbus slave image.
Note — The Bus Master Enable (BM) bit of the PCI_CS register must be set in order for the image to
accept posted writes from an external VMEbus master. If this bit is cleared while there is data in the
VMEbus Slave Posted Write FIFO, the data will be written to the PCI bus. No further data is accepted into
this FIFO until the bit is set.
5.4.1.1 VMEbus Fields
Before the Universe II responds to a VMEbus Master (other than itself), the address must lie between the base
and bound addresses. Also, the address modified must match modifier specified by the address space, access
mode, and type fields. A description of the VMEbus fields for VMEbus Slave Images in presented in Table 5-
6, "VMEbus Fields for VMEbus Slave Image," on page 5-8.
The Universe II’s eight VMEbus slave images (0-7) are bounded by A32 space. Slave images 0 and 5 have a
4 KB resolution. Typically, these images would be used as an A16 image since they provided the finest
granularity. Slave images 1 to 3 and 6 to 8 have a 64 KB resolution. The maximum image size of 4 GB.
Warning —
!
The address space of a VMEbus slave image must not overlap with the address space for the
Universe II’s control and status registers.
5.4.1.2 PCI Bus Fields
The PCI bus fields specifies the mapping of a VMEbus transaction to the appropriate PCI bus transaction and
allows users to translate a VMEbus address to a different address on the PCI bus. The translation of VMEbus
transactions beyond 4 GB results in a wrap-around to the low portion of the address range.
Table 5-6. VMEbus Fields for VMEbus Slave Image
Field Register Bits Description
base BS[31:12] or BS[31:16] in VSIx_BS Multiples of 4 or 64 KBytes (base to
bound: maximum of 4 GB)
bound BD[31:12] or BD[31:16] in VSIx_BD
address space VAS in VSIx_CTL A16, A24, A32, User 1, User 2
mode SUPER in VSIx_CTL Supervisor and /or non-privileged
type PGm in VSIx_CTL Program and/or data
Table 5-7. PCI Bus Fields for VMEbus Slave Image
Field Register Bits Description
Translation Offset TO[31:12] or TO[31:16] in
VSIx_TO Offsets VMEbus slave address to a
selected PCI address