Themis USPIIi-1v, Руководство по оборудованию

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Themis Computer
5-11
5. Universe-IIB Description
5.4.2.3 Control Fields
Through the control fields, the user specify how writes are processes and enable a PCI target image. The PCI
target image is enabled by setting the EN bit.
Posted Writes are performed when the PWEN bit is set and the particular PCI target image is accessed. Posted
writes are only decoded within PCI Memory space. Access from other memory spaces are performed with
coupled cycles, regardless of the setting of the PWEN bit.
Note — For a VMEbus slave image to respond to an incoming cycle, the PCI Master Interface must be
enabled (bit BM in the PCI_CSR register).
5.4.2.4 Special PCI Target Image
A special PCI target image is provided to expedite A16 and A24 transaction. The other eight, standard, PCI
target images are typically programmed to access A32 space. The special PCI target image is a 64 MB space,
located either within memory or I/O space, that is decoded using PCI address lines [31:26]. Its base address is
aligned on 64 MB boundaries and no offsets are provided. Therefore, PCI address information is mapped
directly to the VMEbus. The special PCI target image has a lower priority than any other PCI target image.
Table 5-10. PCI Bus Fields for PCI Bus Target Image
Field Register Bits Description
base BS[31:12] or BS[31:16] in LSIx_BS Translates PCI Bus Address to
VMEbus Address
bound BD[31:12] or BD[31:16] in LSIx_BD 8, 16, 32, or 64 bits
address space LAS in LSIx_CTL A16, A24, A32, User 1, User 2
mode SUPER in LSIx_CTL Supervisor or non-privileged
type PGM in LSIx_CTL Program or data
cycle VCT in LSIx_CTL Single or Block
Table 5-11. Control Fields for PCI Bus Target Image
Field Register Bits Description
image enable EN in LSIx_CTL enable bit
posted write PWEN in LSIx_CTL posted write enable bit