Themis USPIIi-1v, Руководство по оборудованию

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Themis Computer
5-7
5. Universe-IIB Description
The PCI Configuration Base Address 0 and Base Address 1 Registers offsets are 0x010 and 0x014,
respectively. The registers specify the 4KB aligned base address of the 4 KB Universe IIB register space on
PCI. The power-up options determine if the registers are mapped into Memory or I/O space.
5.4 Slave Image Programming
The Universe II recognizes two types of accesses on its bus interfaces: accesses destined for the other bus and
accesses decoded for its own register space.
PCI Bus Size
b
MISC_STAT LCLSIZE 32-bit REQ64#
PCI CSR Image
Space PCI_CSR BM Disabled VA[14]
PCI Register
Access PCI_BS0
PCI_BS1 SPACE Refer to:
Table 5-4 and
Table 5-5 .
VA[1]
PCI Bus Size
c
MISC_STAT LCLSIZE 32-bit REQ64#
PCI CSR Image
Size PCI_CSR BM disabled VA[14]
a. The LAS field will enable the PCI_CSR registers IOS or MS field if the EN FIELD of the LSIO_CTL register is set.
b. As per PCI 2.1 Specification, the PCI Bus Size is loaded on any RST# event.
c. Following the PCI 2.1 Specification, the PCI Bus Size is loaded on any RST# event.
Table 5-4. PCI Configuration Base Address 0 Register (PCI_BS0)
a
a. All other bits are Read 0.
BIts Name Description Reset
State
Access
[31:12] BS Base Address 0 R/W
00 SPACE PCI Bus Address Space: 0 = Memory; 1 = I/O Power-up
Options R
Table 5-5. PCI Configuration Base Address 1 Register (PCI_BS1)
a
a. All other bits are Read 0.
BIts Name Description Reset
State
Access
[31:12] BS Base Address 0 R/W
00 SPACE PCI Bus Address Space: 0 = Memory; 1 = I/O Power-up
Options R
Table 5-3. Universe IIB Power Up Options
Option Register Field Default Pins