Teledyne SP Devices ADQ3 Series, Руководство пользователя

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Classification Revision
Public B
Document ID Print date
20-2507 2022-03-31
6 User Logic 1
The first user logic area (defined in
user_logic1.v
) uses the type 1 bus definition (Section 4.5 ) for its
incoming and outgoing data bus. At this point in the data path (Fig. 3 ), there is no data valid signal
present since every data clock cycle is considered valid. Thus, any custom logic placed in this area must
be designed to output valid data on each data clock cycle.

Important
The first user logic expects valid data to be output on each data clock cycle. There is no data valid
signal at this point in the data path.

Note
The file
framework/dbt1_param.vh
defines constants to use when parametrizing a design in the first
user logic area.
6.1 Default Contents
By default, the first user logic area contains an example of how to interact with the data bus, how to
perform CDC synchronization and a simple test pattern generator. When activated, the test pattern
generator replaces the channel data with a monotonically increasing ramp starting from the base value
specified in BASEVALUE and incrementing by one for each sample in the parallel data word. The pattern
restarts in the next data clock cycle.

Example
With a base value of 1000 and a parallelization of 8, the generator will output
1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1000, 1001, 1002, ...
6.2 Register File
The register file for the first user logic area is defined in the file
user_logic1_s_axi.v
. The default
implementation provides an interface consisting of a read port and a write port to each 32-bit register
separately. The naming follows the perspective of the host computer, i.e. the read port provides the host
computer with data from the firmware and vice versa for the write port.
Adding a new register to the default implementation involves declaring a new set of matching ports and
modifying the logic (in
user_logic1_s_axi.v
) to target this new register when a matching bus transaction
occurs. Refer to the existing design for implementation details.

Important
Failing to implement correct handling of the AXI bus transactions in
user_logic1_s_axi.v
can cause
the host computer to hang when the offending register is accessed.
The register access is controlled in the module instantiating the register file, i.e. (in
user_logic1.v
).
To construct a register with read and write access, connect the two corresponding ports of the register
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