Classification
Revision
Public
B
Document ID
Print date
20-2507
2022-03-31
Impl Critical
Check the
reports/impl_runme.log
for details.
No Clock Critical
Check the
reports/post_impl_no_clock.rpt
for missing clock constraints.
Warnings
These warnings may cause problems and require investigation. Check the corresponding report
file listed in the section for critical warnings for additional details.
Utilization
The total utilization of available instances of LUT, flip-flop (register), block RAM and DSP. This
includes both the framework and user logic designs.
Timing
The importance of timing closure should be well known when working with an HDL designs. Any
failing timing requirements must be fixed before uploading the firmware to the digitizer to avoid
unexpected behavior.
Key values
These parameters are indicators that should be observed to avoid unwanted and/or unexpected
results.
Congestion
Congestion is a measure of shortage of routing resources. A value of 5 or greater indicates
shortage and will lead to significant problems with fulfilling the timing constraints. Please
refer to
UltraFast Design Methodology
] for resolutions.
Maximum fanout
Fanout is the number of nodes driven by a register. The reported number is the maximum
fanout in the design. Fanout are in most cases not a problem since Vivado automatically
replicates registers with high fanout.
Note
Use of
KEEP
,
KEEP_HIERARCHY
,
DONT_TOUCH
,
MARK_DEBUG
or
ASYNC_REG
properties will
prevent the replication of registers.
Control sets
A control signal is a signal to the set/reset and clock enable pin on a register. Registers
that share a common control signal constitute a
control set
. The report provides the per-
centage of the recommended acceptable value given as a guideline in
UltraFast Design
Methodology
]. Excessive usage may lead to difficulty in reaching the timing goals.
Route CPU time
Route CPU time is the process time used during route.
ADQ3 Series FWDAQ Development Kit
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