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20-2507
2022-03-31
4.3.2
CDC Synchronization of a Multi-Bit Signal
The module
cdc_bus
must
be used when it is critical that each bit in a signal is propagated simultaneously.
cdc_bus #(
.WIDTH(WIDTH) // DECIMAL: Number of data bits.
) cdc_bus_datard (
.src_clk_i(src_clk),
// 1-bit input: Source clock.
.dest_clk_i(dest_clk), // 1-bit input: Destination clock.
.src_rst_i(src_rst),
// 1-bit input: Reset dest_data to zero.
// NOTE: It is recommeded to tie src_rst_i low
// unless there is a specific reason to use it.
.src_data_i(src_data),
// WIDTH-bit input: Data to be synchronized.
.src_valid_i(src_valid), // 1-bit input: When asserted src_data_i will
// be synchronized to dest_clk_i.
// NOTE: This signal is ignored while
// src_ready_o is deasserted.
.src_ack_o(src_ack),
// 1-bit output: Asserted when the data has
// been transferred to the destination clock.
.src_ready_o(src_ready), // 1-bit output: While asserted the module is
// ready to accept new data.
.dest_valid_o(dest_valid), // 1-bit output: Asserted when the data has
// been transferred to the destination clock.
.dest_data_o(dest_data)
// WIDTH-bit output: Data synchronized
// to dest_clk_i.
);
Important
In most cases there is no need to clear the output registers in
cdc_bus
and it advised to tie
src_rst_i
low. It
shall not
be connected to a global reset as this will have negative impact on timing.
ADQ3 Series FWDAQ Development Kit
Page 17 of 38
