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20-2507
2022-03-31
4
General Concepts
This section introduces concepts surrounding the development kit based on FWDAQ for ADQ3 series
digitizers. Please refer to the
ADQ3 Series FWDAQ User Guide
] for the base knowledge on how the
digitizer operates. The reader is assumed to be familiar with digital design in general and this section
only serves to highlight some important aspects of digital design with respect to the development kit.
4.1
Parallel Digital Design
More often than not, the FPGA cannot be clocked at the same rate as the incoming data. To handle this
scenario, the logic needs to be implemented to handle several data words per clock cycle, i.e. several
data words in
parallel
. Parallel design is more challenging than its counterpart, where one data word is
processed per clock cycle. Instructing the reader on parallel design is outside the scope of this document
but moving forward, some familiarity with the concept is expected.
4.2
Data Flow
This section provides a brief description of each block in the data path. Fig.
shows an overview of
the data path of FWDAQ for the ADQ3 series digitizers. The data propagates between the modules in
the data path using a bus interface with custom insertion and extraction macros for convenience (see
Section
). Additionally, each module can be accessed from the AXI control bus. These two buses do
not
exist in the same clock domain, meaning any signals transferred from one domain to the other
must
be synchronized to the receiving clock. Refer to Sections
and
for additional details.
Important
Any signals transferred from the control bus clock domain to the data bus clock domain or vice versa
must
be synchronized to the receiving clock.
Trigger control
This module is tasked with inserting
events
on the data bus. The data bus has a single bit indicating
the event itself and bits with additional information such as the position of the event within the
parallel data words (samples).
Gain and offset
The digital gain and offset module is primarily intended for factory calibration but it may also be
accessed by the user, and offers a way of scaling the signal.
Test pattern
This module may be configured to substitute the ADC samples with a synthetically generated
pattern.
DBS
The digital baseline stabilizer, DBS, is designed for pulse signal measurement where high accu-
racy relative to a known baseline is required. Note that DBS is not enabled by default.
ADQ3 Series FWDAQ Development Kit
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