Teledyne SP Devices ADQ3 Series, Руководство пользователя

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Classification Revision
Public B
Document ID Print date
20-2507 2022-03-31
1 Introduction
This document is the user guide for the development kit of the data acquisition firmware for ADQ3 series
digitizers. There are different versions of the development kit depending on the device-to-host interface
and the target number of channels. Make sure the development kit matches the target hardware.
The development kit centers around the user logic areas . These areas target strategic points in the
data path and are specifically intended to contain custom HDL designs.
The first user logic area, UL1, described in Section 6 , operates on the full-rate data stream—before
the trigger information has been decoded to create records. The second user logic area, UL2, described
in Section 7 , operates on complete records, potentially with a reduced sampling rate.
1.1 Definitions and Abbreviations
Table 1 lists the definitions and abbreviations used in this document.
Table 1: Definitions and abbreviations used in this document.
Item Description
ADC Analog-to-digital converter
CDC Clock domain synchronization
Devkit Development kit
DBT1 Data bus type 1
DBT2 Data bus type 2
FWDAQ The data acquisition firmware
GiB Gibibyte ( 1024
3
bytes)
PCB Printed circuit board
RTL Register transfer level
Tcl Tool command language—scripting language used in Vivado.
UL1 User logic 1—the first open FPGA area, see Section 6 .
UL2 User logic 2—the second open FPGA area, see Section 7 .
VHDL VHSIC hardware description language
Verilog Hardware description language
Vivado Xilinx FPGA design suite
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