Classification
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Public
B
Document ID
Print date
20-2507
2022-03-31
7
User Logic 2
The second user logic area (defined in
user_logic2.v
) uses the type 2 bus definition (Section
) for
its incoming and outgoing data bus. At this point in the data path (Fig.
), there is a data
signal
present and the user may modify the output data stream by modulating this signal. However, creating
records of varying sizes is currently not supported but a record of
infinite
length is. The latter type is
created by asserting
and
in the same data clock cycle and new data is added to the
record by asserting
as needed.
should never be asserted for this type of record.
Important
Creating records of varying sizes is currently not supported. Each record output by a specific channel
must either be the same length
or
a record with infinite length. The record length does not need to be
the same value for all channels.
Important
It is crucial that the
output from the second user logic area have the correct
behavior with respect to the data valid signal.
Note
A record with infinite length is created by asserting
and
in the same data clock cycle
and new data is added to the record by asserting
as needed.
should never be
asserted for this type of record.
Note
The file
framework/dbt2_param.vh
defines constants to use when parametrizing a design in the sec-
ond user logic area.
7.1
Default Contents
By default, the first user logic area contains an example of how to interact with the data bus, how to
perform CDC synchronization and a simple test pattern generator. When activated, the test pattern
generator replaces the channel data with a monotonically increasing ramp starting from the base value
specified in
and incrementing by one for each sample in the parallel
word. The pattern
restarts in the next data clock cycle.
Example
With a base value of 1000 and a parallelization of 8, the generator will output
1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1000, 1001, 1002, ...
ADQ3 Series FWDAQ Development Kit
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