Teledyne SP Devices ADQ3 Series, Руководство пользователя

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Classification Revision
Public B
Document ID Print date
20-2507 2022-03-31
bus operations. These are available in Verilog header (
.vh
) files in the
framework/
directory and are
specified in Section 5 . The user must only include the file matching the bus definition in the target user
logic area, i.e.
•
databus_type1_functions.vh
for the first user logic area (UL1) and
•
databus_type2_functions.vh
for the second user logic area (UL2).

Note
In the default design, the source files for the two user logic areas includes the appropriate bus defini-
tions.
Custom logic
Pipeline
Bus
Extracted
fields
Inserted
fields
Fields not
inserted manually
extraction
Bus
insertion
User space
BUS_PIPELINE
Figure 4: A diagram showing the principle of extracting signals from and inserting signals into the
data bus. Any field not inserted manually is subjected to a pipeline delay equal to the value of the
BUS_PIPELINE
parameter.
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