Classification
Revision
Public
B
Document ID
Print date
20-2507
2022-03-31
•
Only one record stop event per record start event may be output. Multiple record start events
without any record stop events will result in data corruption.
•
The record bits are only valid when
is asserted.
•
The record bits may not be asserted in the same data clock cycle.
•
The record bits may be asserted for multiple cycles. Only one of these cycles must have data
asserted.
5.8.2
Number
The record number is an unsigned value that keeps track of the number of records that have been
created since the data acquisition was last started. The value is only valid when
is asserted
and wraps at the maximum value.
5.9
User ID
The user ID is an 8-bit signal with similar function to the
signal. However, this signal
may never be claimed for firmware-specific purposes and is reserved for the user. The value during a
data clock cycle in which
is asserted will propagate to the user space in the host computer
via the record header.
5.10
Differences relative to ADQ14, ADQ7 and ADQ8
This section provides a short list of notable differences in the ADQ3 series digitizers data buses compared
to previous digitizers is provided to help with migrating a design.
•
The data buses are now named
data bus type 1
(DBT1) and
data bus type 2
(DBT2) instead of
real-time
and
reduced rate
.
•
Low-rate channels
have been removed, each channel now instead has parameterized number of
parallel samples and data width.
•
Insert/extract function naming scheme has been changed completely to be more consistent.
•
The record start index and record stop index signals have been added to allow for a record length
granularity of single samples. This also means that a fixed record length can now result in a varying
number of clock cycles between start and stop, depending on which sample the record starts at.
ADQ3 Series FWDAQ Development Kit
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