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Classification

Revision

Public

B

Document ID

Print date

20-2507

2022-03-31

31

30

29

28

27

26

25

24

TESTEN

-

-

-

-

7

6

5

4

3

2

1

0

Range Descriptions

Bit 31 – TESTEN

: Test pattern enable

R/W

If set to 1, the default user logic will replace the data for each channel with a simple test pattern,

see Section

6.1

for additional details. The default value is 0, leaving the data for each channel

unmodified.

Name

UL1BASEVALUE

Offset

2

Default

0

This register contains the base value used by the simple test pattern generator described in Section

6.1

.

31

30

29

28

27

26

25

24

BASEVALUE[31:24]

BASEVALUE[23:16]

BASEVALUE[15:8]

BASEVALUE[7:0]

7

6

5

4

3

2

1

0

Range Descriptions

Bit 31:0 – BASEVALUE

: Test pattern base value

R/W

The base value for the simple test pattern controlled via

TESTEN

. While the range is 32 bits wide,

only as many bits as the channel specifies will be sliced from the register, starting at the least

significant bit. The resulting range will be interpreted as a 2’s complement value.

ADQ3 Series FWDAQ Development Kit

spdevices.com

Page 28 of 38

Содержание ADQ3 Series

Страница 1: ...ADQ3 Series FWDAQ Development Kit User Guide Author s Teledyne SP Devices Document ID 20 2507 Classification Public Revision B Print date 2022 03 31...

Страница 2: ...llel Digital Design 13 4 2 Data Flow 13 4 3 Clock Domain Crossing Synchronization 15 4 3 1 CDC Synchronization of a 1 bit Signal 16 4 3 2 CDC Synchronization of a Multi Bit Signal 17 4 4 AXI Control B...

Страница 3: ...26 6 2 Register File 26 6 3 Default Register File 27 7 User Logic 2 29 7 1 Default Contents 29 7 2 Register File 30 7 3 Default Register File 30 7 4 Port Control 33 7 4 1 Port Impedance 33 7 4 2 ADQ3...

Страница 4: ...03 31 Document History Revision Date Section Description Author B 2022 03 31 Updated for ADQ36 PXIe release TSPD 2021 11 16 7 4 Add section on user logic 2 port control TSPD A 2021 06 21 Initial revis...

Страница 5: ...ate records The second user logic area UL2 described in Section 7 operates on complete records potentially with a reduced sampling rate 1 1 Definitions and Abbreviations Table 1 lists the definitions...

Страница 6: ...dyne SP Devices A license for the Xilinx design tools For current versions of the development kit a license for Vivado 2020 2 is required Minimum tooling is the Vivado Design Edition The Vivado WebPac...

Страница 7: ...assword protected archive the user agrees to the terms of the development kit license The extracted archive is organized as follows Extract root constraints Contains the constraint files for the desig...

Страница 8: ...to previous products since building the user logic areas no longer requires special Tcl commands See Section 3 5 for details 3 3 Setting Up the Project To set up the development kit execute the comma...

Страница 9: ...ns on how to manage the digitizer s firmware 3 5 Working with the Design This section describes the workflow of adding customized logic functions to the digitizer firmware 3 5 1 Typical Design Flow Th...

Страница 10: ...3 6 Analyzing the Implemented Design When the implementation step has completed it is highly recommended to analyze the design to detect the most common issues To do this execute the command devkit_an...

Страница 11: ...a quick overview of the result Fig 2 shows a section from the report A value displayed in red indicates an error that must be addressed Warnings that may require investigation are shown in orange Fig...

Страница 12: ...gestion Congestion is a measure of shortage of routing resources A value of 5 or greater indicates shortage and will lead to significant problems with fulfilling the timing constraints Please refer to...

Страница 13: ...i_aclk AXI control bus clock Check reports exlogic_pcie_axi_aclk rpt for details clk_datapath Data path clock Check reports exlogic_clk_datapath rpt for details data_clk_2x Framework trigger logic clo...

Страница 14: ...The data propagates between the modules in the data path using a bus interface with custom insertion and extraction macros for convenience see Section 5 Additionally each module can be accessed from t...

Страница 15: ...sion Public B Document ID Print date 20 2507 2022 03 31 Figure 3 A block diagram of the data path of FWDAQ The two user logic areas are highlighted in green ADQ3 Series FWDAQ Development Kit spdevices...

Страница 16: ...on the record start and record stop data bus signals respectively Barrel shifter This module rearranges the parallel samples on the bus so that the first entry is the first sample in the record User...

Страница 17: ...nchronization of a multi bit signal using a strobe see Sec tion 4 3 2 These modules should cover most CDC needs and should be used whenever CDC synchronization is called for Refer to Section 4 4 for d...

Страница 18: ...src_valid_i src_valid 1 bit input When asserted src_data_i will be synchronized to dest_clk_i NOTE This signal is ignored while src_ready_o is deasserted src_ack_o src_ack 1 bit output Asserted when t...

Страница 19: ...eir relation in time is kept intact while they are processed by the custom logic Important The bus signals are closely related to each other and it is crucial that their relation in time is kept intac...

Страница 20: ...ons vh for the second user logic area UL2 Note In the default design the source files for the two user logic areas includes the appropriate bus defini tions Custom logic Pipeline Bus Extracted fields...

Страница 21: ...x to navigate this section Example To extract the common timestamp from the type 1 data bus first user logic area use extract_common_timestamp DONT_CARE where DONT_CARE can be any integer in practice...

Страница 22: ...e timestamp is shared between all channels for data bus type 1 and per channel for type 2 5 2 Timestamp Synchronization The timestamp synchronization bus segment is shared between all channels for dat...

Страница 23: ...le The field is a fixed point value in units of samples where the decimal point is to the left of the most significant bit This field is concatenated with the trigger sample index field to get a fixed...

Страница 24: ...the firmware configuration and target device For this purpose each user logic area defines constants which must be used to parametrize a custom design For example UL1 defines the width of one sample a...

Страница 25: ...the valid signal to be periodic it may be asserted and deasserted as needed Clock Valid Record start Record start index 0 Record stop Record stop index 7 data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12...

Страница 26: ...d is reserved for the user The value during a data clock cycle in which record start is asserted will propagate to the user space in the host computer via the record header 5 10 Differences relative t...

Страница 27: ...llel data word The pattern restarts in the next data clock cycle Example With a base value of 1000 and a parallelization of 8 the generator will output 1000 1001 1002 1003 1004 1005 1006 1007 1000 100...

Страница 28: ...mples 6 3 Default Register File This section documents the register file for an unmodified version of the development kit Name UL1ID Offset 0 Default 0x00abcdef This register contains a constant value...

Страница 29: ...ault 0 This register contains the base value used by the simple test pattern generator described in Section 6 1 31 30 29 28 27 26 25 24 BASEVALUE 31 24 BASEVALUE 23 16 BASEVALUE 15 8 BASEVALUE 7 0 7 6...

Страница 30: ...al that the record framing signals output from the second user logic area have the correct behavior with respect to the data valid signal Note A record with infinite length is created by asserting rec...

Страница 31: ...to hang when the offending register is accessed The register access is controlled in the module instantiating the register file i e in user_logic2 v To construct a register with read and write access...

Страница 32: ...31 30 29 28 27 26 25 24 TESTEN 7 6 5 4 3 2 1 0 Range Descriptions Bit 31 TESTEN Test pattern enable R W If set to 1 the default user logic will replace the data for each channel with a simple test pa...

Страница 33: ...The base value for the simple test pattern controlled via TESTEN While the range is 32 bits wide only as many bits as the channel specifies will be sliced from the register starting at the least sign...

Страница 34: ...synchronous to the data clock While the enclosing design ensures that the input signals are CDC synchronized it also assumes that the output and direction signals are synchronous to the data clock The...

Страница 35: ...containing a single pin using single ended signaling ext_sync_i input value of pin 0 ext_sync_o output value of pin 0 ext_sync_direction_o direction of pin 0 GPIOA containing 12 pins using single ende...

Страница 36: ...fix any reported issue Pay special attention to resolve any excessive logic level 2 Review the failing paths and surrounding logic in Vivado s schematic viewer 3 Carefully review that you conform wit...

Страница 37: ...portant Teledyne SP Devices support cannot help with issues localized to the user s custom logic design nor offer training for HDL design concepts 9 1 Debugging on Hardware The section describes one p...

Страница 38: ...ore Connecting to the debug core requires that the mcs file with core has been programmed and that the ltx file is available Depending on the clock signals chosen for the debug core the firmware may h...

Страница 39: ...ignal Processing Devices Sweden AB 21 2539 ADQ3 Series FWDAQ User Guide Tech nical Manual 4 C E Cummings Clock domain crossing CDC design verification techniques using SystemVer ilog in SNUG 2008 proc...

Страница 40: ...SE 583 30 Link ping Sweden Phone 46 0 13 645 0600 Fax 46 0 13 991 3044 Email spd_info teledyne com Copyright 2022 Teledyne Signal Processing Devices Sweden AB All rights reserved including those to r...

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