Tadiran Telecom Coral IPx 500, Руководство по установке

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9-16
Coral IPx 500 Installation Manual
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database to synchronize the PCM clock of the HDC with the digital trunk. In the
absence of an external clock source, the HDC always reverts to an internal clock.
The HDC contains phase-lock circuitry to synchronize the Coral PCM clock to a signal
derived from one of two digital trunk interface cards (PRI23, PRI30, 4TBR, 8TBR, 30T,
30T/x or T1), designated the primary and secondary external clock source. This
feature, called “slaved clock” or “loop-timed” operation, enables the Coral system to
integrate with any digital telephone network in the world. The HDC monitors external
clock signal integrity and switches the system between the primary and secondary
external clock sources or internal HDC clock, as necessary. See
page 9-18, External
Synchronization (ES) Circuit
below for more information.
Digital Tone Generator
The digital tone generator generates the audio call progress tones (dial, busy, ringback,
etc.) that are used to notify the caller of the status of the call. In addition, tones used
during Keyset (FlexSet, GKT, DKT, DST, EKT, VDK, etc.) ringing (except for mute ring,
which is a function of the telephone set itself), DTMF and MFC dialing tones, and test
tone patterns used by diagnostics are also generated by the HDC. These tones are
stored in digital PCM form, in a programmable PROM, and the stored tone patterns
are output directly to the digital PCM bus when required. See
page 9-37, Locally Defined
Tone PROM (U118)
below for more information.
Time Slot Management
The HDC supports two HDLC and eight PCM highways (each PCM highway provides
64 timeslot,) and drives the peripheral buses directly.
Each HDLC and PCM bus operates at a fundamental data rate of 4.096 Mbps. This
data rate allows each HDLC bus sufficient bandwidth to simultaneously control up to
64 peripheral bus controller circuits located on the peripheral cards.
Every PCM highway consists of a transmit bus and a receive bus, each of which are
divided into 64 time slots. Each timeslot is eight bits wide, sampled every 125
microseconds (mS), or 8,000 times per second. This rate matches both American and
European PCM voice transmission rates that are designed to facilitate complete digital
integration with the local telephone network.
The timeslot manager, acting on command by the MCP-IPx system processor, is
responsible for forwarding PCM voice samples from an incoming transmit timeslot
assigned to one port to a complementary outgoing receive timeslot for the recipient
port. Traffic handling capacity of the HDC circuitry is maximized through the use of a
very sophisticated algorithm to avoid timeslot usage conflict.