STMicroelectronics ST10 Series, Руководство по программированию

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ST10 FAMILY PROGRAMMING MANUAL
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2 - STANDARD INSTRUCTION SET
2.1 - Addressing Modes
2.1.1 - Short adressing modes
The ST10 family of devices use several powerful
addressing modes for access to word, byte and bit
data. This section describes short, long and indi-
rect address modes, constants and branch target
addressing modes. Short addressing modes use
an implicit base offset address to specify the
24-bit physical address. Short addressing modes
give access to the GPR, SFR or bit-addressable
memory spacePhysicalAddress = BaseA
∆
x ShortAddress.
Note:
∆
= 1 for byte GPRs,
∆
= 2 for word GPRs
(see Table 1).
Rw, Rb
Specifies direct access to any GPR in the cur-
rently active context (register bank). Both ’Rw’ and
’Rb’ require four bits in the instruction format. The
base address of the current register bank is deter-
mined by the content of register CP. ’Rw’ specifies
a 4-bit word GPR address relative to the base
address (CP), while ’Rb’ specifies a 4 bit byte
GPR address relative to the base address (CP).
reg
Specifies direct access to any (E)SFR or GPR in
the currently active context (register bank). ’reg’
requires eight bits in the instruction format. Short
’reg’ addresses from 00h to EFh always specify
(E)SFRs. In this case, the factor ’
∆
’ equals 2 and
the base address is 00’F000h for the standard
SFR area, or 00’FE00h for the extended ESFR
area. ‘reg’ accesses to the ESFR area require a
preceding EXT*R instruction to switch the base
address. Depending on the opcode of an instruc-
tion, either the total word (for word operations), or
the low byte (for byte operations) of an SFR can
be addressed via 'reg'. Note that the high byte of
an SFR cannot be accessed by the 'reg' address-
ing mode. Short 'reg' addresses from F0h to FFh
always specify GPRs. In this case, only the lower
four bits of 'reg' are significant for physical
address generation, therefore it can be regarded
as identical to the address generation described
for the 'Rb' and 'Rw' addressing modes.
bitoff
Specifies direct access to any word in the
bit-addressable memory space. 'bitoff' requires
eight bits in the instruction format. Depending on
the specified 'bitoff' range, different base
addresses are used to generate physical
addresses: Short 'bitoff' addresses from 00h to
7Fh use 00’FD00h as a base address, therefore
they specify the 128 highest internal RAM word
locations (00’FD00h to 00’FDFEh).Short 'bitoff'
addresses from 80h to EFh use 00’FF00h as a
base address to specify the highest internal SFR
word locations (00’FF00h to 00’FFDEh) or use
00’F100h as a base address to specify the highest
internal ESFR word locations (00’F100h to
00’F1DEh). ‘bitoff’ accesses to the ESFR area
require a preceding EXT*R instruction to switch
the base address. For short 'bitoff' addresses from
F0h to FFh, only the lowest four bits and the
contents of the CP register are used to generate
the physical address of the selected word GPR.
bitaddr
Any bit address is specified by a word address
within the bit-addressable memory space (see
'bitoff'), and by a bit position ('bitpos') within that
word. Thus, 'bitaddr' requires twelve bits in the
instruction format.
Table 1 : Short addressing mode summary
Mnemo Physical Address Short Address Range Scope of Access
Rw (CP) + 2*Rw Rw = 0...15 GPRs (Word) 16 values
Rb (CP) + 1*Rb Rb = 0...15 GPRs (Byte) 16 values
reg 00’FE00h
00’F000h
(CP)
(CP) + 2*reg
+ 2*reg
+ 2*(reg^0Fh)
+ 1*(reg^0Fh) reg
reg
reg
reg = 00h...EFh
= 00h...EFh
= F0h...FFh
= F0h...FFh SFRs
ESFRs
GPRs
GPRs (Word, Low byte)
(Word, Low byte)
(Word) 16 values
(Bytes) 16 values
bitoff 00’FD00h
00’FF00h
(CP) + 2*bitoff
+ 2*(bitoff^FFh)
+ 2*(bitoff^0Fh) bitoff
bitoff
bitoff = 00h...7Fh
= 80h...EFh
= F0h...FFh RAM
SFR
GPR Bit word offset 128 values
Bit word offset 128 values
Bit word offset 16 values
bitaddr Word offset as with bitoff
Immediate bit position bitoff
bitpos = 00h...FFh
= 0...15 Any single bit