STMicroelectronics ST10 Series, Руководство по программированию

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ST10 FAMILY PROGRAMMING MANUAL
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2.2.2 - Minimum state times
The table below shows the minimum number of
state times required to process an instruction
fetched from the internal ROM (
T
Imin (ROM)).
This table can also be used to calculate the mini-
mum number of state times for instructions
fetched from the internal RAM (
T
Imin (RAM)), or
ALE Cycle Times for instructions fetched from the
external memory (
T
Imin (ext)).
Most of the 16-bit microcontroller instructions
(except some branch, multiplication, division and
a special move instructions) require a minimum of
two state times. For internal ROM program execu-
tion, execution time has no dependence on
instruction length, except for some special branch
situations.
To evaluate the execution time for the injected tar-
get instruction of a cache jump instruction, it can
be considered as if it was executed from the inter-
nal ROM, regardless of which memory area the
rest of the current program is really fetched from.
For some of the branch instructions the table
below represents both the standard number of
state times (i.e. the corresponding branch is
taken) and an additional
T
Imin value in parenthe-
ses, which refers to the case where, either the
branch condition is not met, or a cache jump is
taken.
Instructions executed from the internal RAM
require the same minimum time as they would if
they were fetched from the internal ROM, plus an
instruction-length dependent number of state
times, as follows:
– For 2-byte instructions:
T
Imin(RAM) =
T
Imin(ROM) + 4
*
States
– For 4-byte instructions:
T
Imin(RAM) =
T
Imin(ROM) + 6
*
States
Unlike internal ROM program execution, the mini-
mum time
T
Imin(ext) to process an external
instruction also depends on instruction length.
T
Imin(ext) is either 1 ALE Cycle Time for most of
the 2-byte instructions, or 2 ALE Cycle Times for
most of the 4-byte instructions.
The following formula represents the minimum
execution time of instructions fetched from an
external memory via a 16-bit wide data bus:
– For 2-byte instructions:
T
Imin(ext) = 1
*
ACT + ( T
Imin(ROM) - 2)
*
States
– For 4-byte instructions:
T
Imin(ext) = 2
*
ACTs + ( T
Imin(ROM) - 2)
*
States
Note: For instructions fetched from an external
memory via an 8-bit wide data bus, the
minimum number of required ALE Cycle
Times is twice the number for those of a
16-bit wide bus.
2.2.3 - Additional state times
Some operand accesses can extend the execu-
tion time of an instruction
T
In. Since the additional
time T
Iadd is generally caused by internal instruc-
tion pipelining, it may be possible to minimize the
effect by rearranging the instruction sequences.
Simulators and emulators offer a high level of pro-
grammer support for program optimization.
The following operands require additional state
times:
Internal ROM operand reads: T
Iadd = 2
*
States
Both byte and word operand reads always require
2 additional state times.
Table 6 : Minimum instruction state times [Unit = ns]
Instruction
T
Imin
(ROM)
[States]
T
Imin
(ROM)
(20MHz
CPU clk)
CALLI, CALLA
CALLS, CALLR, PCALL
JB, JBC, JNB, JNBS
JMPS
JMPA, JMPI, JMPR
MUL, MULU
DIV, DIVL, DIVU, DIVLU
MOV[B] Rn, [Rm + #data
16
]
RET, RETI, RETP, RETS
TRAP
All other instructions
4
4
4
4
4
10
20
4
4
4
2
(2)
(2)
(2)
200
200
200
200
200
500
1000
200
200
200
100
(100)
(100)
(100)