STMicroelectronics ST10 Series, Руководство по программированию

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ST10 FAMILY PROGRAMMING MANUAL
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3 - MAC INSTRUCTION SET
This section describes the instruction set for the
MAC. Refer to device datasheets for information
about which ST10 devices include the MAC.
3.1 - Addressing modes
MAC instructions use some standard ST10
addressing modes such as GPR direct or #data
5
for immediate shift value. To supply the MAC with
up to 2 new operands per instruction cycle, new
MAC instruction addressing modes have been
added. These allow indirect addressing with
address pointer post-modification. Double indirect
addressing requires 2 pointers, one of which can
be supplied by any GPR, the other is provided by
one of two new specific SFRs IDX
0
and IDX
1
. Two
pairs of offset registers QR0/QR1 and QX0/QX1
are associated with each pointer (GPR or IDX
i
).
The GPR pointer gives access to the entire mem-
ory space, whereas IDX
i
are limited to the internal
Dual-Port RAM, except for the CoMOV instruc-
tion. The following table shows the various combi-
nations of pointer post-modification for each of
these 2 new addressing modes (see Table 27).
When using pointer post-modification addressing
modes, the address pointed to (i.e the value in the
IDX
i
or Rw
n
register) must be a legal address,
even if its content is not modified. An odd value
(e.g. in R0 when using [R0] post-modification
adressing mode) will trigger the class-B hardware
Trap 28h (Illegal Word Operand Access Trap
(ILLOPA)).
In this document the symbols “[Rw
n
⊗
]” and
“[IDX
i
⊗
]” are used to refer to these addressing
modes.
A new instruction CoSTORE transfers a value
from a MAC register to any location in memory.
This instruction uses a specific addressing mode
for the MAC registers, called CoReg. The follow-
ing table gives the 5-bit addresses of the MAC
registers corresponding to this CoReg addressing
mode. Unused addresses are reserved for future
revisions (see Table 28).
Note 1.
IDX
i
can only contain even values. Therefore, bit 0 always equals zero.
Table 27 : Pointer post-modification for [Rw
n
⊗
]” and “[IDXi
⊗
] addressing modes
Symbol Mnemonic Address Pointer Operation
“[IDX
i
⊗
]” stands for
1 [IDX
i
] (IDX
i
) <-- (IDX
i
) (no-op)
[IDX
i
+] (IDX
i
) <-- (IDX
i
) +2 (i=0,1)
[IDX
i
-] (IDX
i
) <-- (IDX
i
) -2 (i=0,1)
[IDX
i
+ QX
j
] (IDX
i
) <-- (IDX
i
) + (QX
j
) (i, j =0,1)
[IDX
i
- QX
j
] (IDX
i
) <-- (IDX
i
) - (QX
j
) (i, j =0,1)
“[Rw
n
⊗
]” stands for [Rw
n
] (Rw
n
) <-- (Rw
n
) (no-op)
[Rw
n
+] (Rw
n
) <-- (Rw
n
) +2 (n=0...15)
[Rw
n
-] (Rw
n
) <-- (Rw
n
) -2 (n=0...15)
[Rw
n
+ QR
j
] (Rw
n
) <-- (Rw
n
) + (QR
j
) (n=0...15; j =0,1)
[Rw
n
- QR
j
] (Rw
n
) <-- (Rw
n
) - (QR
j
) (n=0...15; j =0,1)
Table 28 : MAC register addresses for CoReg
Register Description Address
MSW MAC-Unit Status Word 00000
MAH MAC-Unit Accumulator High 00001
MAS “limited” MAH 00010
MAL MAC-Unit Accumulator Low 00100
MCW MAC-Unit Control Word 00101
MRW MAC-Unit Repeat Word 00110