ST10 FAMILY PROGRAMMING MANUAL
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Internal RAM operand reads via indirect addressing modes:
T
Iadd = 0 or 1
*
State
Reading a GPR or any other directly addressed operand within the internal RAM space does NOT cause
additional state time. However, reading an indirectly addressed internal RAM operand will extend the pro-
cessing time by 1 state time, if the preceding instruction auto-increments or auto-decrements a GPR, as
shown in the following example:
In this case, the additional time can be avoided by putting another suitable instruction before the instruc-
tion
I
n+1 indirectly reading the internal RAM.
Internal SFR operand reads:
T
Iadd = 0, 1
*
State or 2
*
States
SFR read accesses do NOT usually require additional processing time. In some rare cases, however,
either one or two additional state times will be caused by particular SFR operations:
– Reading an SFR immediately after an instruction, which writes to the internal SFR space, as shown in
the following example:
– Reading the PSW register immediately after an instruction which implicitly updates the flags as shown
in the following example:
– Implicitly incrementing or decrementing the SP register immediately after an instruction which explicitly
writes to the SP register, as shown in the following example:
In each of these above cases, the extra state times can be avoided by putting other suitable instructions
before the instruction
I
n+1 reading the SFR.
External operand reads:
T
Iadd = 1
*
ACT
Any external operand reading via a 16-bit wide data bus requires one additional ALE Cycle Time. Read-
ing word operands via an 8-bit wide data bus takes twice as much time (2 ALE Cycle Times) as the read-
ing of byte operands.
External operand writes:
T
Iadd = 0
*
State ... 1
*
ACT
Writing an external operand via a 16-bit wide data bus takes one additional ALE Cycle Time. For timing
calculation of the external program parts, this extra time must always be considered. The value of
T
Iadd
which must be considered for timing evaluations of internal program parts, may fluctuate between 0 state
times and 1 ALE Cycle Time. This is because external writes are normally performed in parallel to other
CPU operations. Thus,
T
Iadd could already have been considered in the standard processing time of
another instruction. Writing a word operand via an 8-bit wide data bus requires twice as much time (2 ALE
Cycle Times) as the writing of a byte operand.
In
: MOV R1, [R0+]
; auto-increment R0
In+1
: MOV [R3], [R2]
; if R2 points into the internal RAM space:
; TIadd = 1
*
State
In
: MOV T0, #1000h
; write to Timer 0
In+1
: ADD R3, T1
; read from Timer 1: TIadd = 1
*
State
In
: ADD R0, #1000h
; implicit modification of PSW flags
In+1
: BAND C, Z
; read from PSW: TIadd = 2
*
States
In
: MOV SP, #0FB00h
; explicit update of the stack pointer
In+1
: SCXT R1, #1000h
; implicit decrement of the stack pointer:
; TIadd = 2
*
States
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