STMicroelectronics ST10 Series, Руководство по программированию

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ST10 FAMILY PROGRAMMING MANUAL
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2.5 - Instruction set ordered by opcodes
The following pages list the instruction set ordered
by their hexadecimal opcodes. This is used to
identify specific instructions when reading execut-
able code, i.e. during the debugging phase.
Notes for Opcode Lists
1. Some instructions are encoded by means of
additional bits in the operand field of the instruction
For these instructions only the lowest four GPRs,
R0 to R3, can be used as indirect address
pointers.
2. Some instructions are encoded by means of
additional bits in the operand field of the instruc-
tion.
Notes on the JMPR instructions
The condition code to be tested for the JMPR
instructions is specified by the opcode. Two mne-
monic representation alternatives exist for some
of the condition codes.
Notes on the BCLR and BSET instructions
The position of the bit to be set or to be cleared is
specified by the opcode. The operand “bitaddr
Q.q
”
(where q=0 to 15) refers to a particular bit within a
bit-addressable word.
Notes on the undefined opcodes
A hardware trap occurs when one of the unde-
fined opcodes signified by ‘----’ is decoded by the
CPU.
x0h - x7h:Rw, #data
3
or Rb, #data
3
x8h - xBh:Rw, [Rw] or Rb, [Rw]
xCh - xFh Rw, [Rw+] or Rb, [Rw+]
00xx.xxxx: EXTS or ATOMIC
01xx.xxxx: EXTP
10xx.xxxx: EXTSR or EXTR
11xx.xxxx: EXTPR
00xx.xxxx: EXTS or ATOMIC
Table 21 : Instruction set ordered by Hex code
Hex- code Number of Bytes Mnemonic Operand
00 2 ADD Rw
n
, Rw
m
01 2 ADDB Rb
n
, Rb
m
02 4 ADD reg, mem
03 4 ADDB reg, mem
04 4 ADD mem, reg
05 4 ADDB mem, reg
06 4 ADD reg, #data
16
07 4 ADDB reg, #data
16
08 2 ADD Rw
n
, [Rw
i
+] or Rw
n
, [Rw
i
] or Rw
n
, #data
3
09 2 ADDB Rb
n
, [Rw
i
+] or Rb
n
, [Rw
i
] or Rb
n
, #data
3
0A 4 BFLDL bitoff
Q
, #mask
8
, #data
8
0B 2 MUL Rw
n
, Rw
m
0C 2 ROL Rw
n
, Rw
m
0D 2 JMPR cc_UC, rel
0E 2 BCLR bitaddr
Q.0
0F 2 BSET bitaddr
Q.0
10 2 ADDC Rw
n
, Rw
m
11 2 ADDCB Rb
n
, Rb
m