STMicroelectronics ST10 Series, Руководство по программированию

Страница: 10 / 174

ST10 FAMILY PROGRAMMING MANUAL
8/172
caddr
Specifies an absolute 16-bit code address within
the current segment. Branches MAY NOT be
taken to odd code addresses.
Therefore, the least significant bit of ’caddr’ must
always contain a ’0’, otherwise a hardware trap
would occur.
rel
Represents an 8-bit signed word offset address
relative to the current Instruction Pointer contents
which points to the instruction after the branch
instruction.
Depending on the offset address range, either for-
ward (’rel’= 00h to 7Fh) or backward (’rel’= 80h to
FFh) branches are possible.
The branch instruction itself is repeatedly exe-
cuted, when ’rel’ = ’-1’ (FF
h
) for a word-sized
branch instruction, or ’rel’ = ’-2’ (FEh) for a dou-
ble-word-sized branch instruction.
[Rw]
The 16-bit branch target instruction address is
determined indirectly by the content of a word
GPR. In contrast to indirect data addresses, indi-
rectly specified code addresses are NOT calcu-
lated by additional pointer registers (e.g. DPP
registers).
Branches MAY NOT be taken to odd code
addresses. Therefore, to prevent a hardware trap,
the least significant bit of the address pointer GPR
must always contain a ’0.
seg
Specifies an absolute code segment number. All
devices support 256 different code segments, so
only the eight lower bits of the ’seg’ operand value
are used for updating the CSP register.
#trap
7
Specifies a particular interrupt or trap number for
branching to the corresponding interrupt or trap
service routine by a jump vector table.
Trap numbers from 00h to 7Fh can be specified,
which allows access to any double word code
location within the address range
00’0000h...00’01FCh in code segment 0 (i.e. the
interrupt jump vector table).
For further information on the relation between
trap numbers and interrupt or trap sources, refer
to the device user manual section on “Interrupt
and Trap Functions”.
2.2 - Instruction execution times
The instruction execution time depends on where
the instruction is fetched from, and where the
operands are read from or written to.
The fastest processing mode is to execute a pro-
gram fetched from the internal ROM. In this case
most of the instructions can be processed in just
one machine cycle.
All external memory accesses are performed by
the on-chip External Bus Controller (EBC) which
works in parallel with the CPU.
Instructions from external memory cannot be pro-
cessed as fast as instructions from the internal
ROM, because it is necessary to perform data
transfers sequentially via the external interface.
In contrast to internal ROM program execution,
the time required to process an external program
additionally depends on the length of the instruc-
tions and operands, on the selected bus mode,
and on the duration of an external memory cycle.
Processing a program from the internal RAM
space is not as fast as execution from the internal
ROM area, but it is flexible (i.e. for loading tempo-
rary programs into the internal RAM via the chip's
serial interface, or end-of-line programming via
the bootstrap loader).
The following description evaluates the minimum
and maximum program execution times. which is
sufficient for most requirements. For an exact
determination of the instructions' state times, the
facilities provided by simulators or emulators
should be used.
This section defines measurement units, summa-
rizes the minimum (standard) state times of the
16-bit microcontroller instructions, and describes
the exceptions from the standard timing.