STMicroelectronics ST10 Series, Руководство по программированию

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ST10 FAMILY PROGRAMMING MANUAL
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Jumps into the internal ROM space: T
Iadd = 0 or 2
*
States
The minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2
additional state times, if the branch target instruction is a double word instruction at a non-aligned double
word location (xxx2h, xxx6h, xxxAh, xxxEh), as shown in the following example:
A cache jump, which normally requires just 2 state times, will be extended by 2 additional state times, if
both the cached jump target instruction and the following instruction are non-aligned double word instruc-
tions, as shown in the following example:
If necessary, these extra state times can be avoided by allocating double word jump target instructions to
aligned double word addresses (xxx0h, xxx4h, xxx8h, xxxCh).
Testing Branch Conditions: T
Iadd
= 0 or 1
*
States
NO extra time is usually required for a conditional branch instructions to decide whether a branch condi-
tion is met or not. However, an additional state time is required if the preceding instruction writes to the
PSW register, as shown in the following example:
In this case, the extra state time can be intercepted by putting another suitable instruction before the con-
ditional branch instruction.
label : .... ; any non-aligned double word instruction
; (e.g. at location 0FFEh)
.... : ....
In+1 : JMPA cc_UC, label ; if a standard branch is taken:
; TIadd = 2
*
States (TIn = 6
*
States)
label : .... ; any non-aligned double word instruction
; (e.g. at location 12FAh)
In+1
:
.... ; any non-aligned double word instruction
; (e.g. at location 12FEh)
In+2 : JMPR cc_UC, label ; provided that a cache jump is taken:
; TIadd = 2
*
States (TIn = 4
*
States)
In : BSET USR0 ; implicit modification of PSW flags
In+1 : JMPR cc_Z, label ; test condition flag in PSW: TIadd= 1
*
State